1. University of Tehran 1 Interface Design DRAM Modules Omid Fatemi (omid@fatemi.net)

2. University of Tehran 2 Dynamic RAM Capacitor can hold charge Transistor acts as gate No charge is a 0 Can close switch & add charge to store a 1 Then open switch (disconnect) Can read by closing switch –Sense amps

3. University of Tehran 3 Hydraulic Analogy Storage Full (1) Empty (0) Pump fills tank to 1 value Pump drains tank to 0 value

4. University of Tehran 4 Reading Tank had a 1 value – raises water level Outside water begins at intermediate level (black wavy line) Tank had a 0 value – lowers water level

5. University of Tehran 5 DRAM Refreshing Refresh –Destructive read –Also, there’s steady leakage –Charge must be restored periodically

6. University of Tehran 6 DRAM Logical Diagram

7. University of Tehran 7 DRAM Read Signaling Lower pin count by using same pins for row and column addresses Delay until data available

8. University of Tehran 8 Standard DRAM Timing

9. University of Tehran 9 DRAM Write Timing

10. University of Tehran 10 PC RAM Interface

11. University of Tehran 11 DRAM Connections in PC

12. University of Tehran 12 Wait State Generation

13. University of Tehran 13 DRAM Refresh Many strategies Logic on chip Here a row counter

14. University of Tehran 14 DRAM Types (refresh) Standard refresh (every 15.6 micro-sec) Extended refresh (every 125 micro-sec)

15. University of Tehran 15 Refresh Methods Burst refresh Distributed refresh

16. University of Tehran 16 Timing Say need to refresh every 64ms Distributed refresh –Spread refresh out evenly over 64ms –Say on a 4Mx4 DRAM, refresh every 64ms/4096=15.6 us –Total time spent is 0.25ms, but spread Burst refresh –Same 0.25ms, but all at once –May not be good in a computer system Refresh takes low % of total time

17. University of Tehran 17 RAS Only Refresh

18. University of Tehran 18 CAS Before RAS Refresh On-board refresh counter applies the row addresses

19. University of Tehran 19 Hidden Refresh

20. University of Tehran 20 RAS Only Refresh in PC

21. University of Tehran 21 Standard DRAM Enhancements Page Mode DRAM –Toggle CAS –Provide column

22. University of Tehran 22 Static Column Mode No CAS Provide Column Assert CS

23. University of Tehran 23 Nibble Mode DRAM Toggle CAS No column address

24. University of Tehran 24 DRAM Burst Access Mode

25. University of Tehran 25 DRAM Timing

26. University of Tehran 26 EDO DRAM Extended Data Out –Data stays when there is no CAS

27. University of Tehran 27 Synchronous DRAM (SDRAM) Has a clock! Common type in PCs late-90s Multiple banks Pipelined –Start read in one bank after another –Come back and read the resulting values one after another

28. University of Tehran 28 Basic Organisation Interleaved Memory Banks (1)

29. University of Tehran 29 Typical Timing Diagram Interleaved Memory Banks (2)

30. University of Tehran 30 SDRAM Timing

31. University of Tehran 31 SDRAM Commands

32. University of Tehran 32 DDR DRAM Double Data Rate SDRAM Transfers data on both edges of the clock The internal databus is twice the width of the external For high speed data integrity –Differential inputs –Differential clocks Currently popular

33. University of Tehran 33 SDR vs. DDR

34. University of Tehran 34 DDR Read

35. University of Tehran 35 RAMBUS DRAM (RDRAM) Another attempt to alleviate pinout limits Many (16-32) banks per chip Made to be read/written in packets Up to 400MHz bus speeds –But DDR doing very well also Each bank, 1MB Each bank 512 rows of 128 dualocts (16 bytes) Only half of banks open at once (sense amp sharing) Multiplexing

36. University of Tehran 36 DRAM Controllers Very common to have chip that controls memory –Handles banks –Handles refresh Multiplexes column and row addresses –RAS and CAS timing Northbridge on PC chip set

37. University of Tehran 37 Pentium 4 cache 80386 – no on chip cache 80486 – 8k using 16 byte lines and four way set associative organization Pentium (all versions) – two on chip L1 caches —Data & instructions Pentium 4 – L1 caches —8k bytes —64 byte lines —four way set associative L2 cache —Feeding both L1 caches —256k —128 byte lines —8 way set associative

38. University of Tehran 38 Comparison of Cache Sizes