1. Memory 2 ©Paul Godin Created March 2008 Memory 2.1

2. USING MEMORY Memory 2.2

3. Memory Memory 2.3

4. Memory in a P System ◊Memory is an integral part of microcomputers. ◊Memory quickly provides the data and instructions the microprocessor needs to process. ◊Memory provides an area where the microprocessor can quickly store processed data. ◊Memory IC’s come in a variety of configurations and are selected based on the microprocessor and the bus structures. Memory 2.4

5. Basic Requirements ◊A microprocessor needs the ability to: ◊Select the memory device ◊Provide the address ◊Decide to read from it, or write to it ◊Ensure it is ready to send or receive the data ◊Memory device circuits need: ◊Tri-state outputs because they are connected to a common bus ◊A decoder to select the appropriate word location ◊Direction control ◊Bus connections to receive or send data ◊An enabling input Memory 2.5

6. Basic Elements Memory Device Data/Instructions AddressSelect Read/Write Memory 2.6

7. Interconnection CPU Memory Address Data Select R/W’ Memory 2.7

8. The 2114 Memory Chip ◊The 2114 chip is an old device but it serves as a good example of a basic memory device ◊Basic Characteristics: ◊Static RAM ◊Non-inverting ◊Common input and output pins ◊TTL compatible Memory 2.8

9. RAM Requirements ◊An input to control direction: a READ or a WRITE operation. ◊An input to select the device. ◊Address input ◊Data input/output A6Vcc A5 A7 A4 A8 A3 A9 A0 D0 A1 D1 A2 D2 CS D3 GndWE 2114 Memory 2.9

10. Read/Write ◊A RAM chip has a read/write selection: ◊If written as : ◊A logic low will Enable Writing to the device ◊A logic high will Enable Reading from the device ◊Write = Input to the memory device ◊Read = Output from the memory device Memory 2.10

11. Chip Select ◊A RAM chip has a Chip Select: ◊If written as : ◊A low will enable the output and enable the input ◊A high will tristate the output and disable the input ◊CS is used to avoid bus contention problems. Memory 2.11

12. RAM Chip Questions 1.What is the word size? 2.How many addressable locations are there? 3.What is the capacity? 4.What connections and input logic is required to read from the device? 5.What are the origins of the signals? A6Vcc A5 A7 A4 A8 A3 A9 A0 D0 A1 D1 A2 D2 CS D3 GndWE 2114 Memory 2.12

13. Function Table CS’WE’DMode HXHi-ZDisabled LLHWrite H LLLWrite L LHD out Read A6Vcc A5 A7 A4 A8 A3 A9 A0 D0 A1 D1 A2 D2 CS D3 GndWE 2114 Memory 2.13

14. Using 2 Memory IC’s ◊The 2114 is a 2 10  4, or 1024  4 bit memory device. Each IC has a 4-bit word size; two ICs can be combined to create an 8 bit word. Memory 2.14

15. Control and Timing Memory Device Data/Instructions AddressSelect Read/Write Memory 2.15

16. Specifications ◊Electrical: ◊Most electrical specifications resemble the TTL-LS specifications. ◊4.75 to 5.25 V for Vcc ◊VOH = 2.4V ◊VOL = 0.4V ◊Exceeds TTL-LS specification for power: ◊ICC = 95 mA at room temperature Memory 2.16

17. Read or Write Process ◊Sufficient time must be provided for the read and the write process to occur without error. ◊Since memory devices rely on a combination of inputs to provide the appropriate output, the specifications for timing can include many values. Input elements that affect output include CS, WR and the address values. All must be present with the right timing for the device to function reliably. Memory 2.17

18. Specifications ◊READ Timing: ◊t RC : Read cycle time. Time for valid data to be present at the output from the time an address is present. The t RC for the 2114 is 300ηs. If words were read one after another, there would need to be 300ηs between these cycles. ◊t ACC : Access time ◊t co : Chip select to output valid Address CS’ Data Output Address t RC Data t ACC t co Memory 2.18

19. Specifications ◊Write Timing: ◊t WC : Write cycle time. Time for valid data to be written to the device reliably. ◊t DS : Data setup time ◊t DH : Data Hold Time ◊t WOT : Time Write to Output Tristate Address CS’ Data Input Address t WC Data t WOT t DH R/W’ t DS Memory 2.19

20. Review Questions ◊Define the following inputs: ◊CS ◊WE ◊R/W ◊D ◊A ◊What typically supplies the address to a memory device? ◊What is the time for a complete memory write cycle? Memory 2.20

21. Internal Structure of Memory ◊Memory is comprised of cells arranged into words ◊Each word is accessed externally via an address. Internally, the address is applied to a decoder, and in turn this decoder enables the specific word to the output. Memory 2.21

22. Address Decoding (ROM) E 1 to 2 decoder (upper) word 1 word 3word 4 word 2 E E E E E E E 1 to 2 decoder (lower) Address buffer OE Word Out Memory 2.22

23. IC Models ◊The 74LS374 is an 8-bit parallel register with tri- state outputs. ◊The 74LS138 is a 3-to-8 decoder Memory 2.23

24. Using the IC Models to Demonstrate Memory Addressing ◊Electronics Workbench File Memory 2.24

25. DRAM ◊DRAM is used an memory in computer systems whereas SRAM is used internally by the microprocessor (cache). ◊Dynamic RAM is inexpensive with greater density and much lower power consumption but is one of the slowest types of memory. ◊The DRAM stores its values as a capacitive charge on tiny MOS capacitors and therefore requires continual refresh to maintain its values. This is a challenge for designing with DRAM. ◊Computer systems may have separate circuitry to refresh the DRAM without using CPU cycles. Memory 2.25

26. DRAM ◊DRAM addressing is somewhat more complex. Each bit is accessed instead of each word as in SRAM. This increases the number of addresses and therefore the number of addresses. ◊Addressing is done in a matrix configuration with the address split between Rows and Columns. Input pins RAS (Row Address Strobe) and CAS (Column Address Strobe) control the input address. Memory 2.26

27. DRAM ◊Representation of DRAM (4x4) Memory 2.27 WIKI CC

28. DRAM ◊A multiplexer is often used to reduce the number of address lines required. ◊Refreshing DRAM is done in 2 manners: ◊Burst mode, where all values of a Row are enabled at once, and access to memory is suspended for this time. ◊Distributed mode, where the refresh is done with memory access functions. This is more complex to manage. Memory 2.28

29. Review ◊DRAM has advantages over SRAM: ◊Low power ◊High density ◊DRAM has some disadvantages over SRAM: ◊More difficult to configure ◊Requires refresh cycles ◊DRAM is popular with microcomputers Memory 2.29

30. ©Paul R. Godin prgodin ° @ gmail.com End Memory 2.30