Work in Progress --- Not for Publication 18 July 2001 Work In Progress – Not for Publication Interconnect Working Group 2001 Draft 18 July 2001 San Francisco Christopher Case

Work in Progress --- Not for Publication 18 July 2001 Work In Progress – Not for Publication Japan Shinichi Ogawa Akihiko Ohsaki Taiwan Calvin Hsueh Shin-Puu Jeng US Robert Geffken Christopher Case Europe Hans Joachim-Barth Joachim Torres Korea Hyeon-Deok Lee Hyun Chul Sohn ITWG Regional Chairs Participating at SEMI West 2001 workshop: Robert Geffken, John Kelly, Jeff Wetzel, Bob Havemann, Harold Hosack, Mike Mills, Shinichi Domae, Christopher Case

Work in Progress --- Not for Publication 18 July 2001 Work In Progress – Not for Publication Agenda Interconnect progression and scope Difficult challenges Technology requirements Section updates: –Conductors –Dielectrics –Planarization –Etch, Strip and Clean –Reliability –System and performance Last words

Work in Progress --- Not for Publication 18 July 2001 Work In Progress – Not for Publication Interconnect Progression 1994 NTRS introduced the need for Cu and low k materials 1997 NTRS describes adoption of these materials 1999 ITRS highlighted –Rapid changes in materials –Materials solutions alone cannot deliver performance - end of traditional scaling in sight 2001 Edition –Materials, integration and interfaces dominate issues –Global wiring concerns require system and design approaches

Work in Progress --- Not for Publication 18 July 2001 Work In Progress – Not for Publication No Moore Scaling!

Work in Progress --- Not for Publication 18 July 2001 Work In Progress – Not for Publication Interconnect scope Conductors and dielectrics –local through global levels Associated planarization Necessary etch, strip and clean Embedded passives Reliability and system and performance issues Ends at the top wiring bond pads Predominantly needs based

Work in Progress --- Not for Publication 18 July 2001 Work In Progress – Not for Publication Wire Via Global (up to 5) Intermediate (up to 4) Local (2) Passivation Dielectric Etch Stop Layer Dielectric Capping Layer Copper Conductor with Barrier/Nucleation Layer Pre Metal Dielectric Tungsten Contact Plug Typical chip cross-section illustrating hierarchical scaling methodology

Work in Progress --- Not for Publication 18 July 2001 Work In Progress – Not for Publication Difficult Challenges Introduction of new materials* Integration of new processes and structures* Achieving necessary reliability Attaining dimensional control Manufacturability and defect management that meet overall cost/performance requirements Dimensional control and metrology Patterning, cleaning and filling high aspect ratios features Integration of new processes and structures Continued introductions of new materials and size effects Identify solutions which address global wiring scaling issues* <65 nm>65 nm * Top three grand challenges

Work in Progress --- Not for Publication 18 July 2001 Work In Progress – Not for Publication Introduction of new materials Near term new barriers and nucleation layers –in situ formed dielectric and metal porous dielectrics ALD potential solutions –Combination of materials and technologies –Many new reliability challenges new materials and interfaces electrical, thermal and mechanical exposure

Work in Progress --- Not for Publication 18 July 2001 Work In Progress – Not for Publication Long term –Continued introduction of materials barriers/nucleation layers for alternate conductors - optical, low temp, RF, air gap alternate conductors, cooled conductors –More reliability challenges –Microstructural and atom scale effects Materials Challenges

Work in Progress --- Not for Publication 18 July 2001 Work In Progress – Not for Publication Dimensional Control 3DCD of features –performance and reliability implications Multiple levels –reduced feature size, new materials and pattern dependent processes –process interactions CMP and deposition - dishing/erosion - thinning Deposition and etch - to pattern multi-layer dielectrics Aspect ratios for etch and fill –particularly DRAM contacts and dual damascene

Work in Progress --- Not for Publication 18 July 2001 Work In Progress – Not for Publication Combinations and interactions of new materials and technologies –interfaces, contamination, adhesion, diffusion, leakage concerns, thermal budget, ESH, CoO Structural complexity –levels - interconnect, ground planes, decoupling caps –passive elements –mechanical integrity –other SOC interconnect design needs (RF) –cycle time Process Integration

Work in Progress --- Not for Publication 18 July 2001 Work In Progress – Not for Publication Technology Requirement Issues Wiring levels including optional levels Reliability metrics Wiring/via pitches by level Planarization requirements Conductor resistivity Barrier thickness Dielectric metrics including effective

Work in Progress --- Not for Publication 18 July 2001 Work In Progress – Not for Publication MPU HP Near Term Years Wiring length per cm 2 excludes global levels Constant reliability still requires improvement in defect density - based on 5 FITS and high performance MPU

Work in Progress --- Not for Publication 18 July 2001 Work In Progress – Not for Publication MPU HP Near Term Years Significant reduction in wiring pitches to match roadmap acceleration Relaxation of feature aspect ratios - due to benefit of Cu

Work in Progress --- Not for Publication 18 July 2001 Work In Progress – Not for Publication MPU HP Near Term Years New combined dishing/erosion metric for global wires Cu thinning due to dishing for isolated lines/pads No significant dishing at local levels - thinning due to erosion over large areas (50% areal coverage)

Work in Progress --- Not for Publication 18 July 2001 Work In Progress – Not for Publication MPU HP Near Term Years Bulk and effective dielectric constants described Cu at all nodes - conformal barriers We will not answer the question - Will CVD or spin-on win?

Work in Progress --- Not for Publication 18 July 2001 Work In Progress – Not for Publication MPU HP Long Term Years Conductor effective resistivity (red) because of scattering effects - research required Zero thickness barrier desirable but not required

Work in Progress --- Not for Publication 18 July 2001 Work In Progress – Not for Publication ITRS Requirement WITH Cu Barrier Effect Of Line Width On Cu Resistivity Courtesy of SEMATECH Conductor resistivity increases expected to appear around 100 nm linewidth - will impact intermediate wiring first - ~ 2006

Work in Progress --- Not for Publication 18 July 2001 Work In Progress – Not for Publication DRAM Near Term Years Contact A/R rises to ~23 in a red challenge - associated with 44 nm non-contacted local wiring pitch Low k introduction is expected to precede Cu by two years

Work in Progress --- Not for Publication 18 July 2001 Work In Progress – Not for Publication Barriers/Nucleation Solutions Barrier engineering –for porous low k –Cu resistivity control –atomic layer deposition - ALD Next generation ECD –Seed repair –Direct ECD on barriers –electrolyte management –possible electroless applications New cleans

Work in Progress --- Not for Publication 18 July 2001 Work In Progress – Not for Publication Conductor Potential Solutions Challenges and changes Seamless fill W conductor Low resistivity Cu process needed to address resistivity increases - address the interface issues CEP combined with Cu ECD Conductors, etch, dielectrics and planarization should address novel/potential cleans

Work in Progress --- Not for Publication 18 July 2001 Work In Progress – Not for Publication Challenges Development and integration of ultra low k materials with acceptable mechanical/thermal properties High k and ferroelectric materials development Fabricating low-temp low-loss SiO 2 optical interconnect to address global wiring issues Dielectric Potential Solutions

Work in Progress --- Not for Publication 18 July 2001 Work In Progress – Not for Publication Etch, Strip and Clean Potential Solutions Many new low and high k materials - may require new chemistries - supercritical CO 2 /solvents, ozone gas/liquid approaches Strip/clean compatibility with these new materials Dimensional control with small features and high A/R Selectivity to etch stops and hard masks Low damage MRAM, FeRAM applications

Work in Progress --- Not for Publication 18 July 2001 Work In Progress – Not for Publication Planarization Solutions CEP - chemically enhanced planarization and spin etch approaches Porous low k will require either alternative planarization or stopping layer/structural enhancements to be compatible with existing planarization techniques

Work in Progress --- Not for Publication 18 July 2001 Work In Progress – Not for Publication Material innovation combined with traditional scaling will no longer satisfy performance requirements –Design, packaging and interconnect innovation needed –Alternate conductors optical, RF, low temperature –Novel active devices (3D or multi-level) in the interconnect Solutions beyond Cu and low

Work in Progress --- Not for Publication 18 July 2001 Work In Progress – Not for Publication Last words Continued rapid changes in materials Must manage 3DCD System level solutions must be accelerated to address the global wiring grand challenge –Cu resistivity increase impact appears ~2006 –materials solutions alone cannot deliver performance - end of traditional scaling –integrated approach with design and packaging