1. November 29, 2001 Santa Clara , CA
2001 ITRS Front End Process
November 29, 2001
Santa Clara , CA

2. FEP Chapter Scope
The scope of the FEP Chapter of the ITRS is to define comprehensive future requirements and identify potential solutions for the key technology areas in front-end-of-line IC wafer fabrication processing

3. FEP Chapter Topics Starting Substrate Materials Surface Preparation
Critical Dimension Etch
MOSFET Isolation, Gate Stack, Doping, and Contact Requirements
High Performance Logic
Low Operating Power Logic (new 2001 addition)
Low Standby Power Logic (new 2001 addition)
DRAM Trench and Stack Capacitor materials and processes

4. FEP Chapter Topics Pre-Metal dielectric layers (new)
FLASH memory materials and processes (new)
FeRAM materials and processes (new)
Non-classical double gate CMOS materials and processes (new)

5. 1999 vs 2001 ITRS Technology Nodes
45 nm gate length was forecasted for year 2008 in 1999 ITRS
32 nm gate length was forecasted for year 2011 in 1999 ITRS
There has been an unprecedented acceleration in MOSFET gate length scaling! In many instances, FEP processes have not kept pace, resulting in compromised device performance expectations. This is reflected in the 2001 FEP & PIDS requirements and difficult challenges

6. FEP Near Term Difficult Challenges
For the years up to and including 2007, with DRAM 1/2 Pitch  65nm, and MPU physical gate length 25nm

7. Near Term Difficult Challenges
1 New gate stack processes and materials for continued planar MOSFET scaling
Remains the number one FEP priority
2 Critical Dimension and MOSFET effective channel length (Leff ) Control
3 CMOS integration of new memory materials and processes
4 Surfaces and Interfaces; structure, composition, and contamination control
5 Scaled MOSFET dopant introduction and control

8. Challenge #1 New Gate Stack Processes- Issues
Extend oxynitride gate dielectric materials to ~0.8-1nm EOT for high-performance MOSFETS
Introduce and integrate high- gate stack dielectric materials for low operating power MOSFETS
Control boron penetration from doped polysilicon gate electrodes
Minimize depletion of dual-doped polysilicon electrodes
Possible introduction of dual metal gate electrodes with appropriate work function (toward end of period)
Metrology issues associated with gate stack electrical and materials characterization

9. Gate Stack Challenges
Direct tunneling currents limit allowable gate oxide thickness reduction, thereby limiting gate capacitance and gate control over channel charge
Electrical depletion of doped polysilicon results in unwanted parasitic capacitance that limits gate control of channel charge, ultimately requiring metal gates
For reference, 1997 ITRS High Performance allowable gate leakage was 1 A/cm2
“red wall” for high performance results from reliability and thickness control
“red wall” for low power results from lower allowed tunneling curents

10. Challenge #2 CD & Leff Control:Issues
Control of gate etch processes to yield a physical gate length that is smaller than the printed feature size, while maintaining  10% 3- control of the combined lithography and etch processes
Control of profile shape, line and space width for isolated, as well as closely-spaced fine line patterns
Control of self-aligned doping introduction process and thermal activation budgets to yield ~ 20% 3- Leff control
Maintenance of CD and profile control throughout the transition to new gate stack materials and processes
Metrology

11. Resist Trim Process Sequence
Photoresist
Hardmask
Gate Poly
Gate Oxide
Substrate
Example
150nm
Example
100nm
Trim
Resist
Open
Hardmask
Etch
Gate Poly

12. Gate Etch Requirements and Challenges
The lithographic, resist trim, and gate etch processes are all assumed to be statistically independent and therefore that the variances (2) are additive
The variances include all random errors, point to point on a wafer, wafer to wafer and lot to lot, but do not include systematic errors

13. Challenge #3 CMOS Integration of New Memory Materials: Issues
Development & Introduction of very high- DRAM capacitor dielectric layers
Migration of DRAM capacitor structures from Silicon-Insulator-Metal to Metal-Insulator-Metal
Integration and scaling of ferroelectric materials for FeRAM
Scaling of Flash inter-poly and tunnel dielectric layers may require high-
Limited temperature stability of high- and ferroelectric materials challenges CMOS integration

14. Technology Migration of Stack Capacitor
130nm nm nm nm
MIS MIM MIM MIM
Metal
Barrier Metal
Perovskite
epi-BST
BST
TiN
Ta2O5
Poly Si

15. Selection from DRAM Stack Capacitor Roadmap

16. Challenge #4 Surfaces & Interfaces: Issues
Contamination, composition and structure control of channel/gate dielectric interface
Contamination, composition and structure control of gate dielectric/gate electrode interface
Interface control of DRAM capacitor structures
Maintenance of surface and interface integrity through full-flow CMOS process
Statistically significant characterization of surfaces having extremely low defect concentrations
Starting materials
Pre-gate cleans

17. Pre-Gate Clean Requirements

18. Challenge #5 Scaled MOSFET Doping: Issues
Doping and activation processes to achieve source/drain parasitic resistance that is less than ~16-20% of ideal channel resistance (=Vdd/Ion)
Control of parasitic capacitance to achieve less than ~19-27% of gate capacitance with acceptable Ion and short channel effect
Achievement of activated doping concentration greater than solid solubility levels in dual doped polysilicon gate electrodes
Formation of continuous self-aligned silicon contacts over shallow source/drain regions
Metrology issues associated with 2-D doping profiling

19. Scaled MOSFET Parasitic Resistance Elements
Accumulation and Spreading resistances
Extension Sheet Resistivity
Contact Junction Sheet Resistivity
Contact Resistivity

20. Ideal MOSFET Contact Scaling
Halo Implant manages SCE from deeper contact
Silicide contact  1/2 of contact region depth
1/2 x in 4 years
Drain Extension Depth Scales with Gate Length
Silicon/Silicide interfacial resistivity is crucial to low contact area resistance
Contact Region Depth Scales more slowly than Gate Length, depending on efficacy of halo

21. PIDS Forecasted High Performance MOSFET Parasitic Elements

22. MOSFET Contact Requirements
The concomitant achievement of drain extension junction depth and sheet resistance poses a major doping challenge
Contact silicide thickness must scale with contact junction depth, making the achievement of a continuous, thin silicide film increasingly difficult to achieve
The contact area is assumed to scale with the ASIC half pitch, resulting in a progressively smaller source/drain contact area. As a consequence the maximum allowable silicide/silicon contact resistivity must be progressively lowered.

23. FEP Long Term Difficult Challenges
For the years beyond 2007, with DRAM 1/2 Pitch < 65nm, and MPU physical gate length <25nm

24. Long Term FEP Challenges
Continued scaling of planar CMOS devices
Introduction and CMOS integration of non-standard double-gate MOSFET devices
These devices may be needed as early as 2007
Increased allocation of long term research resources would be highly desireable
Starting material alternatives beyond 300mm
New memory storage cells, storage devices and memory architectures
Surfaces and Interfaces; structure, composition, and contamination control

25. Challenge #3 Starting Material Alternatives Beyond 300mm: Issues
Future productivity enhancement needs dictate the requirement for a next generation, large substrate material
Historical trends suggest that the new starting material have nominally 2X present generation area, e.g. 450mm
Cost-effective scaling of the incumbent Czochralzki crystal pulling and wafer slicing process is questionable
Research is required for a cost-effective substrate alternative

26. FeRAM Roadmap S. Kawamura (FEP) Here’s a newcomer… November 2001
FEP & PIDS ITWG
FeRAM Roadmap
Here’s a newcomer…
S. Kawamura (FEP)

27. Why FeRAM? FeRAM has the following outstanding features:
*Non-volatility
*Low voltage (power) operation
*High speed
*High endurance
*High integration (Cell structure is similar to DRAM.)

29. Assumptions (1) Feature Size:
0.35mm expected to be available in early 2002, 0.25mm in x0.7 every 1-3 years.
Memory Capacity:
Intend to be aggressive to establish FeRAM market. x4 every 1-3 years.

30. Assumptions (2) Cell Size: planar  stack (x 0.6) 2T2C  1T1C (x 0.6)
Switching Charge Qsw:
Constant DVbitline=140mV for sensing
Qsw=Cbitline x DVbitline
(Planar)
Storage Node
Ferro. Film
Plate
(Stack)
Plate
Ferro. Film
Storage Node

31. Evolution in Cell Structure
Stack Cell (COB)
Stack Cell (CUB)
Bit Line
Planar Cell
3D Capacitor
Bit Line
Bit Line
(Polycide, W, etc.)
Bit Line
(Polycide, W, etc.)
Capacitor
Metal
Word Line
Al, Polycide, W, etc. Al
Ferroelectic Film
(Polycide, W, etc.)
Pt, IrO2, etc.

32. FeRAM vs. DRAM
Giga scale integration will be available with a 3D capacitor
(bit)
Capacity (Mb)
Plate
Ferro. Film
Storage Node 3D
1T1C
Year

33. Qsw and Capacitor Structure
Qsw/2Pr=Required Capacitor Area> Projected Capacitor Size3D.
N.B. Conventional structures can be used for 0.18um if we have Ferroelectric materials with 2Pr=34.5uC/cm2.

34. Issues (1) In order to enjoy (Lambs)
“The Silence of the (other) RAM’s,”
reliability comes first to be focused on,
followed by application and cost.

35. Issues (2) Ferroelectric materials:
Should be stable under thermal budgets.
Usually being used with some dopants.
*) SBT at present gives less than adequate switching charge for 2005 and beyond.
#) Chemical Solution Deposition
PZT:Pb(Zr,Ti)O3, SBT:SrBi2Ta2O9, BLT:(Bi,La)4Ti3O12

36. Issues (3)
Fatigue:
More than 1E+15 is required to compete with SRAM and DRAM. Practical testing is critical.

37. Issues (4) Application: Cost:
Limited to small capacity (embedded) memory for RFID, Smart Card, etc.
Some “killer applications” should be needed to establish FeRAM market.
Cost:
Not competitive due to large cell size. 1T1C and 3D capacitor are mandatory to reduce cost.