1. EMT362: Microelectronic Fabrication Interlevel Dielectric Technology
Ramzan Mat Ayub; SATF 2005
EMT362: Microelectronic Fabrication
Interlevel Dielectric
Technology

2. Ramzan Mat Ayub; SATF 2005
Lecture Objectives
Able to describe the main dielectric materials used in PMD and IMD
Able to describe the main planarization techniques used in MOS
fabrication.

3. FOUR MAIN CHALLENGES IN MULTILEVEL INTERCONNECT
Ramzan Mat Ayub; SATF 2005
FOUR MAIN CHALLENGES IN MULTILEVEL INTERCONNECT
PLANARIZATION OF INTERLEVEL DIELECTRIC
LOW-K DIELECTRIC MATERIALS
FILLING OF HIGH ASPECT RATIO CONTACT HOLES AND VIAS
INTERGRATION OF MANY TYPES OF CONDUCTOR AND DIELECTRIC MATERIALS

4. TERMINOLOGY PASSIVATION METAL-2 VIA-1 METAL-1 PMD IMD OR ILD-1 CONTACT
Ramzan Mat Ayub; SATF 2005
TERMINOLOGY
PASSIVATION
METAL-2
VIA-1
METAL-1
PMD
IMD OR ILD-1
CONTACT

5. REQUIREMENTS OF DIELECTRIC LAYERS
Ramzan Mat Ayub; SATF 2005
REQUIREMENTS OF DIELECTRIC LAYERS
DIELECTRIC LAYERS MUST BE USED TO ELECTRICALLY ISOLATE ONE LEVEL OF
CONDUCTOR FROM ANOTHER IN MULTI LEVEL INTERCONNECT SYSTEMS.
LOW K TO KEEP CAPACITANCE BETWEEN METAL LINES LOW
HIGH BREAKDOWN ( > 5 MV / cm)
NO MOISTURE ABSORPTION
GOOD ADHESION TO ALUMINUM
STABLE AT TEMPERATURES OF ~ 500 C
GOOD CONFORMALITY (STEP COVERAGE)
GOOD THICKNESS UNIFORMITY
EASILY ETCHED

6. DIELECTRIC MATERIALS FOR PMD
Ramzan Mat Ayub; SATF 2005
DIELECTRIC MATERIALS FOR PMD
DOPED SIO2 FILMS BY CVD TECHNIQUE
SILANE / TEOS BASED B(3-5%)P(3-5%)SG MOSTLY USED DIELECTRIC FOR PMD.
REFLOW TEMPERATURE OF <850 C CAN BE ACHIEVED.
IN SUB-MICRON CMOS PROCESS, TEOS BASED CVD OXIDE IS MORE WIDELY USED
COMPARED TO THAT OF THE SILANE BASED.
TYPICAL PMD
USG (UNDOPED SIO2) – TO ACT AS A BARRIER TO THE B & P OUT DIFFUSION
BPSG – EASY TO REFLOW AT LOW TEMPERATURE.

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BPSG B P
USG

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9. DIELECTRIC MATERIALS FOR IMD
Ramzan Mat Ayub; SATF 2005
DIELECTRIC MATERIALS FOR IMD
DOPED SILANE / TEOS BASED SIO2 FILMS
PHOSPHORUS IS ADDED TO;
REDUCE FILM STRESS
MORE RESISTANCE TO WATER
SODIUM GETTERING
CURRENTLY, TEOS BASED FILMS ARE FAVOURABLE DUE TO;
LOWER DEPOSITION TEMPERATURE (< 400C)
BETTER GAP FILLING CAPABILITY (BETTER CONFORMALITY) .

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VOID

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IMD FOR SILANE / TEOS BASED DIELECTRIC FILMS – MIMOS 0.5UM 1-P 2-M PROCESS

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27. Silane oxide (3000A) or Silane Nitride
Ramzan Mat Ayub; SATF 2005
IMD FOR SILANE / TEOS BASED DIELECTRIC FILMS – MIMOS 0.5UM 1-P 2-M PROCESS
TEOS-02 (4000A)
SOG (1500A)
TEOS - O3 oxide (4000A)
Silane oxide (3000A) or Silane Nitride
Barrier for moisture and sodium ion

28. PLANARIZATION OF INTERLEVEL DIELECTRIC FILMS
Ramzan Mat Ayub; SATF 2005
PLANARIZATION OF INTERLEVEL DIELECTRIC FILMS
IMD ti
METAL
No planarization tf
IMD
Smoothing
METAL
IMD
Smoothing & partial
planarization
METAL

29. Complete local planarization
Ramzan Mat Ayub; SATF 2005
IMD
METAL
Complete local planarization
IMD
METAL
Complete global planarization
Planarization factor, β = 1 – (tf / ti)
β = 1, complete planarization
β = 0, no planarization

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32. PROBLEM ASSOCIATED WITH POOR PLANARIZATION
Ramzan Mat Ayub; SATF 2005
PROBLEM ASSOCIATED WITH POOR PLANARIZATION
1. Poor metal step coverage with result in metal thinning
higher resistance
open problem

33. IMD 2. Metal stringers after metal etch.
Ramzan Mat Ayub; SATF 2005
2. Metal stringers after metal etch.
3. DOF limititation for optical lithography – patterning problem
MASK
DOF < 5um
IMD PR
METAL

34. PLANARIZATION TECHNIQUES
Ramzan Mat Ayub; SATF 2005
PLANARIZATION TECHNIQUES
1. Thermal flow (only for PMD)

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As deposited
After reflow

36. 2. TEOS oxide deposit,etch-back and deposit
Ramzan Mat Ayub; SATF 2005
2. TEOS oxide deposit,etch-back and deposit

37. 3. SOG deposit,etch-back and Oxide deposition
Ramzan Mat Ayub; SATF 2005
3. SOG deposit,etch-back and Oxide deposition

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39. 4. Oxide deposition, CMP oxide
Ramzan Mat Ayub; SATF 2005
4. Oxide deposition, CMP oxide

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