XC9000 Series In-System Programming (ISP) and Manufacturing Flows Frank Toth February 20, 2000 ®

Slides:



Advertisements
Similar presentations
Introduction to DFT Alexander Gnusin.
Advertisements

FPGA (Field Programmable Gate Array)
BOUNDARY SCAN.
Logistics & Channel Management
FPGA Configuration. Introduction What is configuration? – Process for loading data into the FPGA Configuration Data Source Configuration Data Source FPGA.
LOGSYS Development Environment of Embedded Systems Tamás Raikovich Béla Fehér Péter Laczkó Budapest University of Technology and Economics Department of.
Chip and Circuit Board Debugging Adam Hoover JTAG.
PLD Technology Basics. Basic PAL Architecture DQ Q CLK OE Fuse.
Lecture 28 IEEE JTAG Boundary Scan Standard
Real-Time Systems Design JTAG – testing and programming.
TAP (Test Access Port) JTAG course June 2006 Avraham Pinto.
SiliconAid Solutions, Inc. Confidential SAJE SiliconAid JTAG Environment Overview – Very Short.
®. Founded in 1991 Industry Leader: Offers industry’s widest range of programming solutions including: low- cost Universal programmers, High performance.
May 8, Peripheral Design Options For USB 2.0 Solutions Dave Thompson Manager of High Speed I/O Development Agere Systems,
Digital Circuit Implementation. Wafers and Chips  Integrated circuit (IC) chips are manufactured on silicon wafers  Transistors are placed on the wafers.
Programmable Solutions in Smart Card Readers. ® Xilinx Overview  Xilinx - The Industry Leader in Logic Solutions - FPGAs & CPLDs —High-density.
1 EE 587 SoC Design & Test Partha Pande School of EECS Washington State University
Scan and JTAG Principles1 Scan and JTAG Principles ARM Advanced RISC Machines.
® ChipScope ILA TM Xilinx and Agilent Technologies.
Xilinx at Work in Hot New Technologies ® Spartan-II 64- and 32-bit PCI Solutions Below ASSP Prices January
CoolRunner ™ -II Low Cost Solutions. Quick Start Training Introduction CoolRunner-II system level solution savings Discrete devices vs. CoolRunner-II.
Section I Introduction to Xilinx
Programmable Solutions in Video Capture/Editing. Overview  Xilinx - Industry Leader in FPGAs/CPLDs High-density, high-speed, programmable, low cost logic.
BS Test & Measurement Technique for Modern Semi-con devices & PCBAs.
Xilinx CPLDs Low Cost Solutions At All Voltages. 0.35u CPLD Product Portfolio Complete Solutions for all Markets 0.18u 0.25u XC9500XL 3.3V 5.0 ns t PD.
Section II Basic PLD Architecture. Section II Agenda  Basic PLD Architecture —XC9500 and XC4000 Hardware Architectures —Foundation and Alliance Series.
File Number Here CPLD Competition. File Number Here Session Objectives  Review Strengths & Weaknesses of key competitors: —Lattice —Vantis —Altera 
® Programmable Solutions in ISDN Modems. ® Overview  Xilinx - Industry Leader in FPGAs/CPLDs —High-density, high-speed, programmable,
Configuration Solutions Overview
Introduction 1 Introduction. 2 Why Programmable Logic ?  Custom logic without NRE —needed for product differentiation  Fast time to market —shorter.
Versus JEDEC STAPL Comparison Toolkit Frank Toth February 20, 2000.
Spartan Series FPGAs. Introducing the Xilinx Spartan Series  New Xilinx solution for high-volume applications  No compromises Performance, RAM, Cores,
J. Christiansen, CERN - EP/MIC
® SPARTAN Series High Volume System Solution. ® Spartan/XL Estimated design size (system gates) 30K 5K180K XC4000XL/A XC4000XV Virtex S05/XL.
® Programmable Solutions in Digital Modems. ® Overview  Xilinx - Industry Leader in FPGAs/CPLDs —High-density, high-speed, programmable,
® Additional Spartan-XL Features. ® Family Highlights  Spartan (5.0 Volt) family introduced in Jan. 98 —Fabricated on advanced 0.5µ process.
ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTEMS Boundary Scan.
Xilinx Programmable Logic Development Systems Alliance Series version 3.
HardWireTM FpgASIC The Superior ASIC Solution
CoolRunner XPLA3 CPLD Overview - August 2000 File Number Here ®
April 20, 2001VLSI Test: Bushnell-Agrawal/Lecture 281 Lecture 28 IEEE JTAG Boundary Scan Standard n Motivation n Bed-of-nails tester n System view.
“Supporting the Total Product Life Cycle”
Tools - Design Manager - Chapter 6 slide 1 Version 1.5 FPGA Tools Training Class Design Manager.
XC9500XL. XC9500XL Overview  Optimized for 3.3-V systems 0.35 micron FastFLASH technology 4 Layers of Metal compatible levels with 5.0/2.5V Reprogramming.
® Xilinx XC9500 CPLDs. ®  High performance —t PD = 5ns, f SYS = 178MHz  36 to 288 macrocell densities  Lowest price, best value CPLD.
Algorithm Change Notice (ACN) What is it? How does it work? Frank Toth September 24, 1999.
WebPOWERED Software Solutions – Spring 2000 WebPOWERED CPLD Software Solutions SPRING OF CY2000.
AT91SAM7 Flash Programming Solutions. ARM-Based Products Group 2  Introduction Flash Programming Terms, Definitions and Glossary  Flash Programming.
© LATTICE SEMICONDUCTOR CORPORATION 2000 Uudet mikropiirit JTAG February Lattice Confidential Lattice Semiconductor The Leader in ISP TM PLDs Presents.
World’s Best CPLDs For Low Power, Portable & Remote Applications.
® XC9500XL CPLDs Technical Presentation. ® XC9500XL Overview  Superset of XC9500 CPLD  Optimized for 3.3V systems —compatible levels.
AVR JTAG Interface The JTAG (Joint Test Action Group) development started about 1985 as a method to test populated circuit boards after manufacture. The.
Summary Remaining Challenges The Future Messages to Take Home.
Xilinx XC9500 CPLDs Technology XC9500 CPLDs DESIGN PROTOTYPING TEST
AVR JTAG Interface The JTAG (Joint Test Action Group) development started about 1985 as a method to test populated circuit boards after manufacture. The.
CPLD Product Applications
XC Developed for a Better ISP Solution
Xilinx Ready to Use Design Solutions
XC9500XV The Industry’s First 2.5V ISP CPLDs
XILINX CPLDs The Total ISP Solution
XC9500XL New 3.3v ISP CPLDs.
XC9500XL New 3.3v ISP CPLDs.
XILINX CPLDs The Total ISP Solution
The performance requirements for DSP applications continue to grow and the traditional solutions do not adequately address this new challenge Paradigm.
FLASH is the Future for CPLDs
Xilinx CPLD Software Solutions
TECHNICAL PRESENTATION
HardWireTM FpgASIC The Superior ASIC Solution
Xilinx Alliance Series
3PL Logistic Software. What is a 3PL? You take the orders. Your third-party logistics provider (3PL) fulfils them. It’s that simple and if it’s seamless,
Presentation transcript:

XC9000 Series In-System Programming (ISP) and Manufacturing Flows Frank Toth February 20, 2000 ®

®  Flexible, efficient, pin-locking architecture  Industry standard JTAG/ISP  High endurance  High performance  PC & WS software XC9000 Series: Developed for a Better ISP Solution Process Technology Chip Architecture Software

®  Easy prototyping: —Minimize fragile package handling —Develop - program - test - redesign - reprogram in an integrated software environment  System integration: —Advanced debugging tools via JTAG  Manufacturing: —Pre-production: allow last minute design changes —High volume: integrate device programming & board-level test  Field upgrades: —Allows for design upgrading/reconfiguration in the field PrototypingSystem Integration Field Upgrades Manufacturing Pre-production Manufacturing High Volume ISP Supports the Product Life Cycle

® XILINX CPLDs Driving the ISP Evolution  Complete support of the ISP designer’s Product Life Cycle  Delivers new FLASH technology benefits to CPLDs  Provides industry’s best pin-locking CPLD at lowest price  Complete “state-of-the-art” software support  CPLDs key part of the Xilinx “total logic solution”

® XC9000 Series Supports Multiple Programming Methods  ISP via PC/Workstation download cable —Prototype programming/debug —Functional test/programming in manufacturing  Hardware programmer —Data I/O, BP Micro, & others...  ATE —HP, GenRad, Teradyne, IFR  Microprocessor/Microcontroller download —C-Code embedded support

® Benefits of ISP in Manufacturing  Maximize: —Profit —ROI for ATE time —Flexibility —Manufacturing efficiency  Minimize: —Risk —Overall manufacturing time —Board/part damage —Rework —Inventory management —Time-to-Market

® Four Typical Manufacturing Flows  Assemble  PC Program ATE Test  Assemble ATE Program/ Test  Assemble ATE Test PC Program  Preprogram Assemble ATE Test

® Flow 1 Assemble/PC Program/ATE Test Programming Considerations PC Cost Handling fallout Programming personnel Cable Floor space Fixture development Xilinx Solutions JTAG Programming Software Download Parallel/Serial Cables Win 95/NT support Concurrent (multiple simultaneous) Programming Assemble Blank Chips Program on PC Test on ATE & Burn-in Inventory & Ship

® Flow 2 Assemble/ATE Program & Test Programming Considerations ATE memory More tester time Xilinx ATE Solutions HP 3070 Support GenRad GR228X Support Teradyne Spectrum & Z1800 IFR Series 4200 Uses Industry Standard SVF files Full JTAG Support Assemble Blank Chips Program & Test on ATE Burn-in Inventory & Ship

® Flow 3 Assemble/ATE Test/PC Program Programming Considerations PC Cost Handling fallout Programming personnel Cable Floor space Fixture development Xilinx Solutions JTAG Programming Software Download Parallel/Serial Cables Win 95/NT support Concurrent Programming Assemble Blank Chips Test on ATE Program on PC Inventory & Ship Functional Test

® Flow 4 Preprogram/Assemble/ATE Test Programming Considerations Programming cost Inventory cost Insertion handling fallout Programmer cost Xilinx Solutions 3rd Party Programmer Certification Xilinx HW130 Programmer Distribution Programming Center Certification Board Assembly of Programmed Chips Inventory & Ship Test on ATE

® Robust JTAG Instruction Set Industry standard 4-pin IEEE JTAG Design, debug, chip test & programming through JTAG Basic JTAG support: EXTEST, SAMPLE/PRELOAD, BYPASS, CLAMP Industry-leading extended JTAG manufacturing support USERCODE: built-in version control capability IDCODE: identification of manufacturer, part number, silicon revision INTEST: drive/read internal logic HIGHZ: all outputs in high impedance mode, sophisticated interconnect test ISP CLAMP (XC9500XL): clamps outputs while programming

® XC9000 Series Utilizes Industry Standard JTAG Chains XC9000 Series FPGA uP DSP ASIC XC9000 Series TDI TDO TMS TCK

® Xilinx Supports All Flows Key Attribute Flow Embedded Option Mfg Time X X X Fewer steps Inventory Savings XXX X Lower cost Yield Enhancement X Lower Handling Fallout Benefits/ Comments HW Cost Savings X X No need for PCs, cables, handlers Floor Space Savings XXLess equipment needed Process Adaptability XXXEasy upgrades during prototyping phase Outsource Programming XXConsistent with well known mature flow Use of Subcontractors More focus on core competency X XX X

® Xilinx Provides Total ISP Manufacturing Solution  Many ways to program XC9000 Series in manufacturing  Xilinx provides support for all flows —resources, tools, alliances  XC9000 Series has most complete JTAG support  GOAL: Make customers successful in applying ISP to their manufacturing process

® Xilinx Third Party Solutions Automatic Test Equipment JTAG Programming & Debug