1. Introduction to DFT
Alexander Gnusin

2. Internal Scan Concept
Used to get access to all internal chip registers:
Scan inputs
Func inputs
Func outputs
Scan outputs

3. MuxScan Design MuxScan: use one clock for Func and Test mode
TE signal selects mode
In test mode reg-to-reg combinatorial logic is bypassed TE D D D TE TE TI TI Q TI CK CK

4. Boundary Scan Principles
Intent: Include board-level test functionality into chip-level devices
Solution: Use serial shift register wrapped around the boundary of chip
Operation Modes:
Serial Shift mode
Parallel Capture / Update mode

5. Boundary Scan Architecture
Boundary registers
Tap
Controller
Instruct. Reg
Bypass Reg
Misc Regs
Mode Control
SOUT IN
OUT
TDI
SIN
TMS
TCK
TRST
TDO
ShiftDR
ClockDR
UpdateDR

6. PCB with IEEE 1149.1 test bus TMS, TCK and TRST connected in parallel
Tap
Tap
TDI
TMS
TCK
TRST
TMS, TCK and TRST
connected in parallel
TDI , TDO - sequentially
Tap
Tap
TDO

7. Test Bus Signals
TCK – Test clock, the master clock during the boundary-scan process
TDI – Test Data Input, used to shift in Data or Instructions
TDO – Test Data Output, used to shift out Data
TMS – Test Mode Selector, used to control FSM in TAP Controller
TRST – Optional TAP Controller asynchronous reset

8. Board and Chip Test Modes
External Test Mode – to test board interconnect:
Mode Control
Mode Control
SOUT
SOUT IN
OUT IN
OUT
Application Logic
Application Logic
SIN
SIN
ShiftDR
ClockDR
UpdateDR
ShiftDR
ClockDR
UpdateDR

9. Board and Chip Test Modes (Cont)
Sample Test Mode: Sampling Data during normal chip operation:
Mode Control
Mode Control
SOUT
SOUT IN
OUT IN
OUT
Application Logic
SIN
SIN
ShiftDR
ClockDR
UpdateDR
ShiftDR
ClockDR
UpdateDR

10. Board and Chip Test Modes (Cont)
Internal Test Mode: drive chip inputs and capture chip outputs using boundary registers (Functional Isolation)
Mode Control
Mode Control
SOUT
SOUT IN
OUT IN
OUT
Application Logic
SIN
SIN
ShiftDR
ClockDR
UpdateDR
ShiftDR
ClockDR
UpdateDR

11. Tap Controller
FSM of Tap Controller is controlled by only one signal, TMS:
Test-Logic-Reset 1 1 1 1
Run Test/Idle
Select DR-Scan
Select IR-Scan 1
Capture-DR
Capture-IR
Shift-DR
Shift-IR 1 1
Exit-DR
Exit-IR 1 1
Update-DR
Update-IR 1 1

12. Tap Controller States
Test-Logic-Reset : Boundary Scan disabled, normal functional mode
Run Test/Idle : Internal BIST test runs
Capture-DR : Data loaded in parallel into TDR (Test Data Register) selected by current instruction (ClockDR pulse, ShiftDR = 0)
Shift-DR : Shift Data in TDR, selected by current instruction (ClockDR pulse, ShiftDR = 1)
Update-DR : Update data on the output of TDR, selected by current instruction (UpdateDR pulse)
Mode Control
SOUT IN
OUT
SIN
ShiftDR
ClockDR
UpdateDR

13. TAP Controller Instructions
Bypass: to bypass current chip, when targeting the other one
Highz: turns all device output off and inserts the bypass register between TDI and TDO.
Clamp: the contents of the boundary register control the state of output pins while the bypass register is connected between TDI and TDO
Extest : to test circuitry external to the chip (board interconnect)
Sample: sample data on IO Pads into the boundary register
Intest: To apply a test vector to the chip via boundary-scan path and capture logic response
RunBIST: Allows self-test execution on the chip

14. Built-in Self-Test (BIST)
BIST - Capability of a circuit to test itself
Test Pattern Generation Types:
Exhaustive Testing (for n inputs, 2n tests)
Pseudorandom Testing (weighted Test Generation)
Pseudoexhaustive Testing (divide by logic cones and test them in parallel, but each one exhaustively)
Pseudo Random Pattern Generator (PRPG) – multioutput device that generates pseudorandom output patterns (based on LFSR, Linear Feedback Shift Register)
Multiple-Input Signature Register (MISR) – multi-input device that compresses a series of input patterns into unique signature

15. Weighted PRPG
PRPG: produces pseudorandom data without replacement (all vectors are unique).
Constant-Weight PRPG: probability to get “1” for each output is constant (Example : equal number of “1” and “0” in each word => weight = 0.5)
PRPG can adjust weights adding combinatorial logic to the outputs:
0.5
0.25
0.75
Clk
Clk

16. Generic LBIST Architecture
First, PRPG issues N pseudorandom tests, where N – maximal internal scan chain length.
Second, series of Functional Clock pulses is issued
for DC test, the same test clock as for PRPG is used
For AC test, functional clock must be provided with real frequency
Third, changed data is shifted to MISR and compressed signature is created (using the same N number of test clocks)
LBIST Controller
PRPG
Clk Te
Func inputs
Func outputs
Test (N clocks) Func Test (N clocks)
Signature
MISR

17. LBIST Design Issues
In order to produce constant signature, we need to remove all X – sources from design:
Assign constant logic value to all Primary Inputs
Isolate memories (or all elements without scan chains)
Isolate PLLs
LBIST can be initiated and signature can be read out using user-defined instructions of TAP controller
Long simulation times to produce signature – use of cycle-based simulator

18. TPI – Test Points Insertion
Two type of test points :
Control Points (CP) are Primary Inputs or Scannable Register Outputs to enhance controlability
Observation Points (OP) are Primary Outputs or Scannable Register Inputs to enhance observability
Problem: G not controlable C1 G C1 C1 G’ G C1
cp1
cp2
Problem: G not observable C1 G C1 C1 G C1 D

19. Scannable Register Insertion
Control Point:
Observation Point:
To TI of next
register only TE OP TE
D=0 CP D TI TI CK CK

20. Memory BIST
Embedded Memories use non-scannable registers – how to test them?
Getting access to all memory pins from PI and PO is expensive…
Better solution – add Memory BIST Controller to generate Test Patterns and to observe Test Responses from memory
Two ways to add controller :
Separate for each memory array (encapsulation) - less wires, more area
Shared for the number of memory arrays - less area, but much more wires
Memory Test is initiated using TAP Controller
Test In …
RAM …
Din
RAM …
Dout
MBIST
Test Out

21. Logic Vision Memory BIST
Logic Vision solution: reducing the number of SRAM test vectors to one:
Parallel
Test Vectors:
Sequential
Test Vectors:

22. Pin Sharing
More internal scan chains for faster testing – more test Iopads
Internal Test Scan Input/Output pads are disconnected on the board
The pads number in the chip is limited.
Solution: Share Functional and Test pins
Mode Control
Mode Control
SOUT
SOUT
OUT IN
OUT IN
SIN
SIN
ShiftDR
ClockDR
UpdateDR
ShiftDR
ClockDR
UpdateDR
Test Mode
Scan Out

23. JTAG for functional debugging
Allscan:
“Freeze” the chip and get access to ALL registers data
Modify Some registers data and and continue in functional mode
Implementation:
Serial connection of all Internal Scan chains between TDI and TDO
Test Clock is produces from JTAG clock (TCK)
Clocks Control – no clock glitches when “freezing” the chip SI
Core Logic SO
Func Clock
JTAG Clock
Allscan
Result Clock
TDI
TDO
Glitch, can destroy data in registers