Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic SEQUENTIAL LOGIC.

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Presentation transcript:

Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic SEQUENTIAL LOGIC

Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic

Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Positive Feedback: Bi-Stability

Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Meta-Stability Gain should be larger than 1 in the transition region

Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic SR-Flip Flop Q S R Q S R Q Q Q Q Q Q

Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic JK- Flip Flop

Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Other Flip-Flops

Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Race Problem

Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Master-Slave Flip-Flop

Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Propagation Delay Based Edge-Triggered

Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Edge Triggered Flip-Flop

Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Flip-Flop: Timing Definitions

Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Maximum Clock Frequency

Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic CMOS Clocked SR- FlipFlop

Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Flip-Flop: Transistor Sizing

Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic 6 Transistor CMOS SR-Flip Flop

Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Charge-Based Storage

Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Master-Slave Flip-Flop

Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic 2 phase non-overlapping clocks

Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic 2-phase dynamic flip-flop

Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Flip-flop insensitive to clock overlap

Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic C 2 MOS avoids Race Conditions

Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Pipelining

Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Pipelined Logic using C 2 MOS

Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Example

Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic NORA CMOS Modules

Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Doubled C 2 MOS Latches

Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic TSPC - True Single Phase Clock Logic

Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Master-Slave Flip-flops