A.Kashchuk Muon meeting, CERN Presented by A.Kashchuk

A.Kashchuk Muon meeting, CERN LHCb muon front-end chip Why 2 chips? CARIOCA negative by user’s eyes CARIOCA positive 1.What I like and accept 2.What I don’t like and can not accept

A.Kashchuk Muon meeting, CERN It is possible: “Bipolar”

A.Kashchuk Muon meeting, CERN In order to satisfy specific requirements of the LHCb experiment, it has been suggested in January 2000 (to Burkhard and Pierre) to start designing own LHCb Muon ASIC for MWPC using submicron CMOS It was clear already in Dec.1999, that we’ll not find perfect chip...

A.Kashchuk Muon meeting, CERN Innovation in the CMOS amplifier is the active feedback (see P.Jarron et al.,1995) SPICE model of the Current Amplifier based on the active feedback Input Output It provides in CMOS fast shaping and low noise at high Cdet

A.Kashchuk Muon meeting, CERN I like that  LHCb Muon front-end chip is designed in 0.25 micron CMOS technology of IBM;  It based on the new active feedback schematics which provides in CMOS fast shaping and low noise at high Cdet;  It is radiation hard;  It has single power supply +2.5V and low power consumption;  It can also be applied for RPC;  It can be optimized for negative and positive input polarities I like also that  Its further integration with DIALOG chip can provide compact and cost-effective solution for any number of channels/board needed in various regions of the LHCb Muon System

A.Kashchuk Muon meeting, CERN Input polarity definition in CARIOCA chip versions: Positive version nMOS Negative version pMOS -If=Iin+IbiasIf=Iin+Ibias Input current must be added to bias current to maximize dynamic range

A.Kashchuk Muon meeting, CERN I suggest changes in schematics of the CARIOCA preamplifiers  Stability margin is not enough;  Optimization of CMOS transistor parameters within feedback loop has to be done;  Cfeed should be avoided I’ll show problems (and my statements) What do not like

A.Kashchuk Muon meeting, CERN Equivalent circuit and its impulse response: G5=42.35mA/V, G6=1.1mA/V, G7=52.6uA/V, Cfeed=400fF, capacitors CARIOCA negative Parameters taken from chip: Model is ringing even at small Cdet Qin =1fC

A.Kashchuk Muon meeting, CERN G5=42.35mA/V, G6=1.1mA/V, G7=52.6uA/V, Cfeed=400fF, capacitors Model is unstable at Cdet=10-100pF CARIOCA negative (cont.) Cdet is increased Being connected to SPB, all 16 channels of CARIOCA negative generate 80 MHz at any threshold Note: similar response has been reproduced on real schematics with increasing G7

A.Kashchuk Muon meeting, CERN Equivalent circuit and its impulse response: G5=42.35mA/V, G6=1.4mA/V, G7=19uA/V, Cfeed=400fF, capacitors CARIOCA positive Parameters taken from chip: Model is close to instability

A.Kashchuk Muon meeting, CERN Both versions will be stable at reduced G7 (factor10)

A.Kashchuk Muon meeting, CERN As shown, without Cfeed it is unstable again Cfeed=0.4pF introduces dynamic capacitor of about 120 pF

A.Kashchuk Muon meeting, CERN It’ll be stable without Cfeed at reduced G6 (factor 10) Excellent response Excelent response Cdet=0-1000pF, 50% amplitude reduction at Cdet=1000pF Excellent impulse response Only G5 is taken from chip

A.Kashchuk Muon meeting, CERN As a result: CARIOCA negative can not be used; CARIOCA positive has small stability margin Note: feedback loop in CARIOCA has been designed incorrectly in both preamplifiers

A.Kashchuk Muon meeting, CERN I suggest changes in schematics Preamplifiers (cont.)  Current-mirrors from preamplifiers to the shaper stage (providing about 3mV/fC gain) must be avoided;  E xisting gain (25mV/fC) has to be used;  Proposed schematics will also reduce voltage spread propagated to the next stages

A.Kashchuk Muon meeting, CERN Negative version Vout to shaper Existing voltage gain has to be used, it will also reduce voltage spread propagated to the next stages Positive version

A.Kashchuk Muon meeting, CERN  One ASIC versus two

A.Kashchuk Muon meeting, CERN Solution 1: by increasing Ibias Increased Ibias=60uA instead of 6uA Iin (dummy input) To the existing connections within CARIOCA chip How I have modified positive version to work with negative signals:

A.Kashchuk Muon meeting, CERN MWPC on cosmics equipped by the positive board with the negative input signal TDC spectrum at 3.15kV (OR of 3 wire strips 6mm width x 25cm length each one) Gas 40Ar/50CO2/10CF4, Th=+/-200mV Sigma 2.9ns within requirements

A.Kashchuk Muon meeting, CERN Both main and dummy inputs will be used in this version to save threshold polarity Only one bias current is ON Solution 2: by switching Ibias polarity

A.Kashchuk Muon meeting, CERN Shaper  Time constants cancelled in CARIOCA: 9 and 80ns I did not see how looks difference of the real signal and its approximation by sum of the exponents implemented in CARIOCA;  I’ll show (see below), that another time constants have to be cancelled, using another optimization criterion I suggest changes in schematics

A.Kashchuk Muon meeting, CERN Pulse width vs HV measured with 241Am-source shows HV=3.15kV Bursts of pulses occur when tail crosses threshold Average pulse width shows tail

A.Kashchuk Muon meeting, CERN ASDQ++ has no such ‘defect’ up to 3.3kV Rise starts at kV! Carioca+/- Carioca+ ASDQ++ max

A.Kashchuk Muon meeting, CERN e.g. better approximation at large times and another criterion : max error 5% at 0<t<15ns and 0.2% at 15ns<t<10us Various signal approximations and optimization criteria can be used Note: in order to provide correct ion tail cancellation we must measure signal I(t) in MWPC at operational gas and final chamber performance with 55Fe-source +/-5% +/-0.2% within noise Poles to be cancelled time in ns (log scale)

A.Kashchuk Muon meeting, CERN Base Line Restorer (BLR must reduce base line fluctuations introduced by another sources)  Spread of DC levels produced by BLR on discriminator inputs must be avoided; (See Werner’s report)

A.Kashchuk Muon meeting, CERN Discriminator  Differential thresholds should be changed to single polarity;  Threshold has to be common for even and odd channels;  Hysteresis has to be studied better (can be reduced on board)

A.Kashchuk Muon meeting, CERN  Very good general architecture of CARIOCA chip (dummy channel followed differential stages) has been implemented rather bad  ‘Bipolar’ solution ‘One ASIC instead of two’ is real one. We have to work effectively to implement many improvements for submission in July 2002 Conclusion