Presentation on theme: "AIDA design review Davide Braga Steve Thomas ASIC Design Group 9 January 2008."— Presentation transcript:
AIDA design review Davide Braga Steve Thomas ASIC Design Group 9 January 2008
AIDA design review2 Design status from September 2007 Analogue design progress: Effect of limited front-end gain Amplifier optimisation for high gain wide output swing linearity Next steps: Final analogue design Digital gate-level design Top-level integration and layout Overview
9 January 2008AIDA design review3 Top-level digital design implemented (based on ERD) Provides control of power-on reset, reset of peak-hold/comparator peak-hold gating sparse read-out, address generation Design needs to be extended for pre-amp, shaper and clamp reset. Digital design currently on hold. Status of digital design in September
9 January 2008AIDA design review4 Status of analogue design in September: Analogue channel, with peak-hold and gating Functional blocks for pre-amp, shaper, peak-hold, comparator Blocks based on earlier designs, with some optimisation Original pre-amp design has relatively low open-loop gain (~5000). Low gain causes channel to channel coupling via parasitic capacitance.
9 January 2008AIDA design review5 PreAmplifier High gain → Large output swing →small C f → reduced input coupling effect improved charge collection improved linearity improved SNR: improved Slew Rate / timing performances small area
9 January 2008AIDA design review6 Vout=1V Vin=-200 V A=-5000 Input coupling effect Cable has high interstrip capacitance Fluctuation of Vin causes coupling of charge between adjacent channels Effect is worse than voltage step across AC coupling capacitor A=-5000 Ccable2 Ccoup Cf Vout= Vin*Ccable/Cf Ccable1
9 January 2008AIDA design review7 Input coupling effect Response in adjacent channels to be < 0.25% FSR: if FSR=1V, C coup =58pF →ΔV<38μV →A OL >35000 Input voltage for different preamplifier gain (C f =1pF) Two stage amplifier
9 January 2008AIDA design review8 Charge Collection Charge not collected from the detector: C det equivalent input capacitance C f (A OL +1) QSQS
9 January 2008AIDA design review9 Two Stage Amplifier + pMOS Source Follower 1 st stage:pMOS folded cascode 2 nd stage:pMOS common source Output stage:source follower, to provide high drive capability nMOS S.F.: affected by nonlinearity because of the body effect pMOS S.F.: source connected to the bulk → good linearity V in V ref V out
9 January 2008AIDA design review10 Corner Analysis The amplifier’s performances must fulfil the specifications in the whole range of operating conditions: Open loop gain:A OL >40000 Stability:Phase Margin=φ M >55° Temperature:-20° <T° <+85° Supply Voltage: 3V<V dd <3.6V Process parameter: 45 cases 405 corner simulations, each one must present: Example of corner analysis
9 January 2008AIDA design review11 Corner Analysis Stability issue solved by making compensation independent of process and temperature Good stability but poor output swing, due to the big variation in the threshold voltage for some of the corners: 1.3V<V out <1.78V biasSF biasCS biasRC inCS inSF from current reference
9 January 2008AIDA design review12 Two Stage Amplifier + nMOS Source Follower The output stage has intrinsic nonlinearity but, being inside the feedback loop, its effect is mitigated by the high open loop gain Sensitivity of the overall gain to the open loop gain’s variation: nMOS Source Follower non linearity (W.Sansen: Analog Design Essentials)
9 January 2008AIDA design review13 Biasing circuit The biasing circuit doesn’t require any setting or trimmer The same preamplifier can work with both polarities, depending only on the value of the reference input voltage V ref.
9 January 2008AIDA design review14 Positive polarity Vref=0.1V 62450 <A OL < 252500 A OL_ typical =162700 55.9° <φ M < 78.1° φ M_typical =67.4° Negative Polarity Vref=1.6V 62250 <A OL < 212600 A OL_typical =130700 61.1° <φ M < 77.5° φ M_typical =71.5° Results
9 January 2008AIDA design review15 Vref=0.1V Results Vref=1.6V
9 January 2008AIDA design review16 Results Between the two extreme operating points (V ref =0.1V and V ref =1.6V), the preamplifier has better performances →good stability DC gain Phase Margin For instance, for the middle range value: Vref=0.85V 79700 <A OL < 263500 A OL_typical =167500 59.4° <φ M < 79.1° φ M_typical =71°
9 January 2008AIDA design review17 Feedback Capacitor Output swing: from 0.1V to 1.6V→ ΔVout MAX =1.5V
9 January 2008AIDA design review18 Linearity The linearity of the preamplifier (loaded by an ideal shaper) has been measured sweeping the value of the input current Input CurrentAmplifier Output
9 January 2008AIDA design review19 Linearity (Vref=0.1V) The highlighted event is a simulation inaccuracy due to error propagation. Nevertheless, the integral non linearity is <0.04% over a wide range of 1.5V
9 January 2008AIDA design review20 Linearity (Vref=1.6V) The highlighted event is a simulation inaccuracy due to error propagation. Nevertheless, the integral non linearity is <0.09% over a wide range of 1.5V
9 January 2008AIDA design review21 Input Voltage Step The high open loop gain limits the voltage step on the input node, anyway a voltage spike is always present because of the finite bandwidth of the amplifier. Its magnitude is strongly dependant on the collection time of the detector. Collection time=410nsCollection time=110ns
9 January 2008AIDA design review22 Next steps: Amplifier optimisation based on measured detector response (plasma model for detector) Investigation of polarity switching Top-level control circuit design Physical layout Target of April for design submission?