The transmission line circuit block used in Cadence Major Blocks and Peak Detector Sections of Channel Equalization Techniques for Ethernet Communication.
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Presentation on theme: "The transmission line circuit block used in Cadence Major Blocks and Peak Detector Sections of Channel Equalization Techniques for Ethernet Communication."— Presentation transcript:
The transmission line circuit block used in Cadence Major Blocks and Peak Detector Sections of Channel Equalization Techniques for Ethernet Communication Systems Undergraduate Summer Research Grant Program Department of Electrical Engineering Texas A&M University Lizhuo Wang Undergraduate Student Texas A&M University Dr. Jose Silva-Martinez Assistant Professor Texas A&M University ABSTRACT Fast communication signals sent from one computer to another across the lines of transmission are degraded because of the reflection at the receiver. It is shown that equalizing the impedance at both ends will further improve the data transmission. A control loop using an active impedance matching device based on a chip solution is a feasible solution, which could save hundreds of thousands of dollars over the lifetime of a single product line and millions of dollars in all. the main idea is to compare the voltage difference between the two ends of the transmission line and minimize the value by adjusting the impedance at both ends based on the value of the difference as a feedback. The project targets on designing fundamental building blocks, and mainly focuses on the peak detector part. The transmission line model, peak detector and error amplifier building blocks for on-chip matching component of the Ethernet communication system are scratched out. It will connect to a A/D converter and a control part to adjust the ends capacitances in the transmission line stage. Transmission Line Model CONCLUSION AND FUTURE WORK CADENCE SIMULATION RESULTS: The signal degradation is minimized when both the emitter and receiver capacitances are around 1/3 of the capacitance of the transmission line capacitance in the T-model. Magnitude: capacitance as parametric sweep Group delay with the parametric simulation The figure on the right shows that the output difference from the peak detector has the ability to track the input amplitude. The latest version of the peak detector building block is shown on the left. No need for the DC reference part in the end. Large Capacitor for small ripples. It is clearly shown in the right side graph that the difference of the peak values between the two wave signals is presented, which means it is functional as peak detectors. To prove that the difference between detected values and the difference between real peak values have a direct relationship. Plotted with several sets of simulation results A direct relationship, which means the detection will surely make sense and can be used for later stages. The values in filters are not required to be reasonable for on-chip design because the reference part on the right will not be put onto chips The early design of the peak detector with reference counterpart. Comparison of the peak detector transfer characteristic as determined by Cadence simulations, measurements at 80M Hz Peak detector building block Outputs of the peak detector stages Plot of real peak difference vs. detected difference with the input signal amplitude from 40mV to 300mV Buffer and Error Amplifier The acquired peak values from the pervious stage will be compared by subtracting each other in a differential amplifier circuit. Both amplifier output and detector outputs are graphed below. Matched perfectly = this stage works properly! The schematic of the whole circuit The differentiation building block Peak Detector The peak detector circuit is show below. The signal input is provided at the left side, while output includes the peak value of the AC amplitude and the DC component brought by the transistor. a symmetrical structure with low pass filters is implemented to eliminate the DC effect. It will connect to the peak detector stage where a DC voltage is held. So a buffer is needed. PMOS transistor for bringing the gate impedance the minus end of the ideal amplifier is connected to a DC supply voltage around the input level. Applications DESIGN *Pictures from Mr. Richard Kamprath’s Master Thesis