1. Analog Building Blocks for P326 Gigatracker Front-End Electronics
Sorin Martoiu, Univ./INFN Torino

2. Outline Front-End Cell Building Blocks CFD analysis
“CMOS” implementation
Passive Filter
Scaling
Dynamic Offset cancellation
Coincidence discriminator vs. zero-crossing discriminator w/ leading-edge hysteresis
Preamplifier
Single-ended to differential block
Overall performance
Additional blocks
Conclusion & Discussion

3. Front-End Cell Building BlocksPA
SEDB
CFDF
ZCD DD
PA Preamplifier
SEDB Single-ended to differential buffer
CFCF CFD filter
ZCS Zero-crossing discriminator
DD Digital driver

4. Chip Floorplan Proposal
Cell0
Cell1
Readout
CellN
Digital noise

5. CFD analysis Ideally zero time-walk No delay-line in CMOS
Bipolar signal
Hdelay(s) = HLP(s)
Hdiscr(s)
Delay f
ZC discriminator
Ideally zero time-walk
No delay-line in CMOS
LP filter instead
σt = σnoise/(dV/dt) time-walk ~ offset/(dV/dt)

6. CFD analysis
Increasing filter order performance approaches ideal delay line CFD

7. “CMOS” Differential Implementation

8. Filter Scaling kT/C noise floor => high C for low noise
high peak current from input nodes
non-uniform filter – C scales up from in to out nodes, w/ RC = constant
Non-uniform scaling
Uniform scaling

9. Dynamic Offset Compensation
I+I
I-I
Offset cancellation
Low-pass feedback => high-pass overall transfer => reduce low-frequency noise (1/f noise)

10. Dynamic Offset Compensation

11. Coincidence discriminator
Delay f
ZC discriminator
Noise produces inherent noise switching at output of ZCD
Need parallel leading-edge discriminator to mask noise switching
Noise switching is not eliminated

12. ZCD w/ hysteresis
ZCD “arms” when the bipolar signal crosses a certain threshold
Switching noise is eliminated
Additional fast block w/o offset compensation => may introduce some time walk

13. Front-End Cell Building BlocksPA
SEDB
CFDF
ZCD DD
PA Preamplifier
SEDB Single-ended to differential buffer
CFCF CFD filter
ZCS Zero-crossing discriminator
DD Digital driver

14. Preamplifier Peaking time 5ns Gain 40mV/fC
Output noise < fF (150e- ENC)
Non-linearity < 1.5%

15. SED Buffer High drive current ~ 100uA GBW > 500MHz Good linearity
Good CMRR
Class AB differential opamp with CMFB and CMFF

16. SED Buffer

17. CFDF + ZCD Layout

18. Status Full channel simulations: jitter: 100ps rms (1fC signal)
time-walk: 200ps max

19. Power Consumption Block IDD (uA) P@Vdd=1.2 (uW) PA 70 84 SEDB 250 300
ZCD
110
132 DD
Total
500 uA
600 uW

20. Potential problems Disturbances at sensitive nodes Parasitics
SEDB
CFDF
ZCD DD
Disturbances at sensitive nodes
Parasitics
decrease bandwidth
induce non-linearity
Input and/or output skews – affect measurement

21. Timewalk