1. Differential Amplifiers

2.  What is a Differential Amplifier ? Some Definitions and Symbols  Differential-mode input voltage, v ID, is the voltage difference between v 1 and v 2.  Common-mode input voltage, v IC, is the average value of v 1 and v 2. Therefore v ID = v 1 - v 2 and v IC = (v 1 + v 2 ) / 2  Differential Amplifier: A differential amplifier is an amplifier that amplifies the difference between two voltages and rejects the average or common mode value of the two voltages. v1v1 v2v2 v out Symbol for a Differential Amplifier

3. The output voltage of the differential amplifier can be expressed in terms of its differential-mode and common-mode input voltage as - V out = A VD v ID + A VC v IC = A VD (v 1 -v 2 ) + A VC (v 1 +v 2 )/2  Where A VD = differential-mode voltage gain A VC = common-mode voltage gain v out v IC v ID /2

4.  Common mode rejection ration (CMRR) CMRR = A VD A VC CMRR - a measure of performance For ideal diff Amp – A VC is zero and hence an infinite CMRR  Input Common-mode range (ICMR) ICMR is the range of common-mode voltages over which the differential amplifier continues to sense and amplify the difference signal with the same gain. Typically, ICMR is defined as common-mode voltage range over which all MOSFETs remain in the saturation region.  Offsets: Output offset voltage (V OS (out)) : It is defined as the voltage which appears at the output of the Diff Amp when the inputs terminal are shorted. Input offset voltage (V OS (in)) : It is equal to the output offset voltage divided by the differential voltage gain - V OS = (V OS (out) / A VD )

5.  LARGE SIGNAL ANALYSIS CMOS differential amplifier using NMOS transistors Configuration of M 1 and M 2 is known as source coupled pair. M 3 and M 4 are a typical implementation of current sink I SS. Large signal analysis starts with the assumption that M 1 and M 2 are perfectly matched i D1 i D2 I SS I bias V Bulk M4M4 M2M2 M1M1 M3M3 V DD v G2 v G1 v GS1 v GS2

6.  Transconductance Characteristics of the Differential Amplifier Defining Equations: v ID = v GS1 -v GS2 = (2i D1 /  ) 1/2 - (2i D2 /  ) 1/2 and I SS = i D1 + i D2 Solution of above equations: i D1 =  SS    v ID 2  SS    v ID 4  SS 2  i D2 =  SS    v ID 2  SS    v ID 4  SS 2  and 1/2 Valid for v ID < (2I SS /  ) 1/2 Differentiating i D1 w r t v ID and setting v ID =0V gives differential transconductance of the Diff Amp as g m =  (i D1 )/  (v ID ) at [V ID =0] = (  I SS /4) 1/2 = (K’ 1 I SS W 1 /4L 1 ) 1/2 i D /I SS (v ID /(I SS /  ) 0.5 ) 1.0 0.8 0.6 0.4 0.2 i D1 i D2 0.0 1.414

7.  Voltage Transfer Characteristics of the Differential Amplifier CMOS differential Amplifier using a current-mirror load Differential-in, differential-out transconductance g md is given as: g md =  (i out )/  (v ID ) at [V ID =0] = (K’ 1 I SS W 1 /L 1 ) 1/2 = Twice of g m M2M2 M1M1 M5M5 V DD v G2 v G1 v GS1 v GS2 M4M4 M3M3 V bias i D1 i D2 i D3 i D4 I SS i out v out

8.  Voltage Transfer Characteristics of the Diff Amp (cont.) 5 4 3 2 1 0 -0.500.51.0 v ID (volts ) V out (volts) V IC =2V M2 saturated M2 active M4 saturated M4 active Region of operation of the transistors: M2 is saturated when, v DS2 >= v GS2 -V TN  v out – V S1 >= V IC - 0.5v ID – V S1 – V TN  v out >= V IC – V TN Where we have assumed that the region of transition for M2 is close to v ID = 0V. Similarly M4 is saturated when, v SD4 >= v SG4 - !V TP !  V DD - v out >= V SG4 - !V TP !  v out =< V DD – V SG4 + !V TP !

9.  Differential Amplifier Using p-channel Input MOSFETs V DD M1M1 M5M5 v G2 v G1 V bias i D1 i D2 i D3 i D4 I DD i out M3M3 M4M4 M2M2 V out

10.  Input Common Mode Range (ICMR) ICMR is found by setting v ID = 0 and varying v IC until one of the transistors leaves the saturation region. Highest Common Mode Voltage: There are two paths from V IC to V DD – (1) From G1 through M1 and M3 to V DD and (2) From G2 through M2 and M4 to V DD For path (1), V IC (max) = V G1 (max) =V G2 (max) = V DD – V SG3 –V DS1 (sat)+ V GS1 = V DD –V SG3 +V TN1 For path (2), V IC (max)’ = V DD – V SD4 (sat) – V DS2 (sat) + V GS2 = V DD –V SD4 (sat) +V TN2 ………………… is more than the first case. Therefore V IC (max) = V DD –V SG3 + V TN1 Lowest Common Mode Voltage: V IC (min) = V DS5 (sat) + V GS1 = V DS5 (sat) + V GS2 We have assumed that V GS1 = V GS2 during changes in the input common mode voltage.

11.  SMALL SIGNAL ANALYSIS  Analysis of the Differential-Mode of the Differential Amplifier Simplifies to When both sides of the amplifier are perfectly matched then - ac ground G1 G2 v id v g1 v g2 1/gm3 rds3 rds1 D1=G3=D3=G4 D2=D4 i3i3 gm1v gs 1 S3 gm2v gs 2 i3i3 rds4 i out ’ S4 v out rds2 rds5 S1= S2 Small signal model for the CMOS differential Amplifier (exact model)

12.  Analysis of the Differential-Mode of the Differential Amplifier (cont.) Differential Transconductance: i out ’ = {(g m1 g m3 r p1 )/(1+g m3 r p1 )}v gs1 - g m2 v gs2 = g m1 v gs1 – g m2 v gs2 = g md v id Where g m1 = g m2 = g md, r p1 = r ds1 !! r ds3 and i out ’ designates the output current in a short circuit. We assume that the output is ac short. G1 G2 v id v gs2 1/gm3rds3rds1 D1=G3=D3=G4D2=D4 i3i3 g m1 v gs1 S1=S2=S3=S4 g m2 v gs2 i3i3 rds2 rds4 i out ’ v gs1 Simplified equivalent model

13.  Analysis of the Differential-Mode of the Differential Amplifier (cont.) Therefore differential voltage gain: A v = (v out /v in ) = { g md / (g ds2 +g ds4 ) } If we assume that all transistors are in saturation and replace the small signal parameters of g m and r ds in terms of their large-signal model equivalents, we achieve A v = (v out /v in ) = (K’ 1 I SS W 1 /L 1 ) 1/2 ( 2 +  )(I SS /2) = 2 ( 2 +  ) K’ 1 W 1 I SS L 1 1/2 Note that the small signal gain is inversely proportional to the square root of the bias current. To calculate unloaded differential voltage gain: r out = 1/(g ds2 +g ds4 ) = r ds2 r ds4

14.  Common–Mode Analysis for the Current Mirror Load Differential Amplifier In an ideal case when there are no mismatches, the current-mirror load rejects any common-mode signal. So the common-mode gain of the differential amplifier with a current mirror load is ideally zero. In order to show how to analyze the small signal, common-mode gain of the differential amplifier, we will consider a different circuit. Let’s see …

15.  Common–Mode Analysis for the Differential Amplifier (an illustration) Let us consider the circuit shown below: Differential-Mode Analysis: v o1 /v id = - (g m1 /2g m3 ) and v o2 /v id = + (g m2 /2g m4 ) M2M2 M1M1 V DD M4M4 M3M3 v o1 vo2vo2 V id /2 Differential-mode circuit M2M2 M1M1 M5M5 V DD M4M4 M3M3 V bias v1v2 I SS v o1 vo2vo2 General circuit

16.  Common–Mode Analysis for the Diff Amp (an illustration) …(cont.) Common-mode analysis: M2M2 M1M1 M5M5 V DD M4M4 M3M3 V bias v1v2 I SS v o1 vo2vo2 General Circuit M2M2 M1M1 M5/2 V DD M4M4 M3M3 V bias I SS /2 v o1 vo2vo2 M5/2 I SS /2 v ic Common-mode circuit

17.  Common–Mode Analysis for the Diff Amp (an illustration) …(cont.) Small-signal model for common-mode analysis - g m1 v gs1 r ds 3 v o1 r ds 1 2r ds 5 vicvic v gs 1 1/g m 3 For simplification let’s assume that r ds1 is large and can be ignored. v gs1 = v ic – 2g m1 r ds5 v gs1 The single ended output voltage, v o1, as a function of v ic is v o1 v ic = - g m1 [r ds3 (1/g m3 )] 1 + 2g m1 r ds5 = - (g m1 /g m3 ) 1 + 2g m1 r ds5 = - (g ds5 /2g m3 ) CMRR = (g m1 /2g m3 ) (g ds5 /2g m3 ) = g m1 r ds5

18.  Frequency Response of the Differential Amplifier (differential-mode) After some approximations we will finally get - V out (s) V in (s) = g m1 g ds2 + g ds4  s +  2 First order approximation Where  2 = [(g ds2 + g ds4 )/ C 2 ] C 2 = C bd2 + C bd4 + C gd2 + C L M2M2 M1M1 M5M5 V DD v G2 v G1 v GS1 v GS2 M4M4 M3M3 V bias v out C bd 2 C gd 2 CLCL C bd 4 C gd 4 C gd 1 C bd 3 C bd 1 C gs3 + C gs4

19. Slew Rate: Maximum output-voltage rate (either positive or negative) For the differential amplifier with current mirror as loads, SR = I SS C Where C is the total capacitance connected to the output node. Note that slew rate can only occur when the differential input signal is large enough to cause I SS to flow through only one of the differential input transistors. For MOSFET differential amplifier SR can be + 2mV or more.  Slew Rate of the Differential Amplifier

20.  Solved Example: Design of a CMOS Differential Amplifier with a Current Mirror Load DESIGN CONSIDERATIONS: Constraints: Power Supply Technology Temperature Specifications Small-signal gain Frequency response ICMR Slew Rate Power Dissipation WHAT IS DESIGN ? The design in most CMOS circuits consists of an architecture represented by a schematic, W/L values of transistors, and dc currents. A v = g m1 R out  -3dB = 1/R out C L V IC (max) = V DD – V SG3 + V TN1 V IC (min) = V DS5 (sat) + V GS1 = V DS5 (sat) + V GS2 SR = I SS /C L P diss = (V DD – V SS ) times all dc currents flowing from V DD to V SS RELATIONSHIPS:

21.  Design: continued STEPS: 1. Choose I 5 to satisfy the slew rate knowing C L or the power dissipation. 2. Check to see if R out will satisfy the frequency response, if not change I SS or modify circuit. 3. Design W 3 /L 3 (W 4 /L 4 ) to satisfy the upper ICMR. 4. Design W 1 /L 1 (W 2 /L 2 ) to satisfy the small signal differential gain. 5. Design W 5 /L 5 to satisfy the lower ICMR. 6. Iterate where necessary. Specs: V DD = -V SS = 2.5 V, SR > 10V/  s (C L = 5pF) f -3dB > 100kHz (C L = 5pF), A v = 100V/V, -1.5V < ICMR < 2V and P diss < 1mW. Given parameters: K’ N = 110  A/V 2, K’ P = 50  A/V 2, V TN = 0.7 V, V TP = -0.7V, N = 0.04V -1, P = 0.05V -1. EXAMPLE:

22.  Design: continued Solution 1. Slew rate gives, I SS > 50  A. P diss gives I SS < 200  A. 2. f -3dB  Rout < 318k  From here and using R out =[2/(( N + P )I SS ], we get I SS > 70  A. Let’s pick I SS = 100  A. 3. V IC (max) = V DD – V SG3 + V TN1 gives W 3 /L 3 = (W 4 /L 4 ) = 8 4. A v = 100V/V = g m1 R out  W 1 /L 1 = (W 2 /L 2 ) = 18.4 5. V IC (min) = V SS + V DS5 (sat) + V GS1  W 5 /L 5 = 300 6. Since W 5 /L 5 is too large, we should increase W 1 /L 1 to reduce V GS1 and allow a smaller W 5 /L 5. If W 1 /L 1 = 40, then W 5 /L 5 = 9. Note: Here A v increases to 111.1 V/V, which should be Okay. Thank You