Viterbi Decoder: Presentation #9 M1 Overall Project Objective: Design a high speed Viterbi Decoder Stage 9: 29 nd Mar Chip Level Simulation Design Manager: Yaping Zhan Omar Ahmad Prateek Goenka Saim Qidwai Lingyan Sun

Status , Integrated Circuits Design Project Design Proposal: (Done) Architecture Proposal: (Done) Gate level Design: (Done) Component Layout (DRC & LVS): (Done) Component Simulation: (Done) Chip Layout: (Done) Spice simulation of entire chip Critical Path Simulation(Done) Entire Chip Simulation(Still Running)

Schematic: top level , Integrated Circuits Design Project Viterbi Decoder clk rst In_valid In_data Out_valid Out_data

18-525, Integrated Circuits Design Project Layout – Entire Chip

Critical Path Extraction , Integrated Circuits Design Project DFF MUX COMP + + DFF + + +

Input Pattern Selection Input_0Input_ Find all possible input patterns , Integrated Circuits Design Project

Input Pattern Selection DFF MUX COMP + + Worst case pattern for adder: and Worst Case pattern for Comp: two Inputs are the same: vs Decision : Use input pattern and for both adders , Integrated Circuits Design Project

Waveform Testing Speed: 500 MHz , Integrated Circuits Design Project

Propagation Delay , Integrated Circuits Design Project Propagation Delay: 437ps

Rising Time , Integrated Circuits Design Project Rising Time: 750 ps

ACS Simulation: Got DC to GND errors Whole Chip Simulation: Still Running , Integrated Circuits Design Project

Questions