Shift Registers Discussion D5.2 Example 31. 4-Bit Shift Register qs(3) qs(2) qs(1) qs(0) if rising_edge(CLK) then for i in 0 to 2 loop s(i) := s(i+1);

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Presentation transcript:

Shift Registers Discussion D5.2 Example 31

4-Bit Shift Register qs(3) qs(2) qs(1) qs(0) if rising_edge(CLK) then for i in 0 to 2 loop s(i) := s(i+1); end loop; s(3) := data_in; end if; Behavior

library IEEE; use IEEE.STD_LOGIC_1164.all; entity shift4 is port( data_in : in STD_LOGIC; clk : in STD_LOGIC; clr : in STD_LOGIC; q : out STD_LOGIC_VECTOR(3 downto 0) ); end shift4; architecture shift4 of shift4 is begin process(clr,clk) variable qv: STD_LOGIC_VECTOR(3 downto 0); begin if clr = '1' then qv := "0000"; elsif clk'event and clk = '1' then for i in 0 to 2 loop qv(i) := qv(i+1); end loop; s(3) := data_in; end if; q <= qv; end process; end shift4; shift4.vhd

shift4 simulation

-- Example 31: 4-bit shift register library IEEE; use IEEE.STD_LOGIC_1164.all; entity ShiftReg is port( clk : in STD_LOGIC; clr : in STD_LOGIC; data_in : in STD_LOGIC; q : out STD_LOGIC_VECTOR(3 downto 0) ); end ShiftReg;

architecture ShiftReg of ShiftReg is signal qs: STD_LOGIC_VECTOR(3 downto 0); begin -- 4-bit shift register process(clk, clr) begin if clr = '1' then qs <= "0000"; elsif clk'event and clk = '1' then qs(3) <= data_in; qs(2 downto 0) <= qs(3 downto 1); end if; end process; q <= qs; end ShiftReg;

clock_pulse

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity clock_pulse is port ( inp, cclk, clr: in std_logic; outp: out std_logic ); end clock_pulse; clock_pulse

architecture clock_pulse_arch of clock_pulse is signal delay1, delay2, delay3: std_logic; begin process(cclk, clr) begin if clr = '1' then delay1 <= '0'; delay2 <= '0'; delay3 <= '0'; elsif cclk'event and cclk='1' then delay1 <= inp; delay2 <= delay1; delay3 <= delay2; end if; end process; outp <= delay1 and delay2 and (not delay3); end clock_pulse_arch; clock_pulse