Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Sedra/Prentice Hall, Saint/McGrawHill,

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Presentation transcript:

Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Sedra/Prentice Hall, Saint/McGrawHill, Weste/Addison Wesley]

Last time: Lecture 03: CMOS fabrications How do transistors make up different CMOS gates? Today: Fabrication of CMOS gates

What needs to be fabricated?

Top view

Fabrication Target: Inverter GND VDD

Gate layouts is decomposed into primitives layouts that would be printed in sequence

Wafer preparation

Photolithography is used to print desired patterns on the wafer UV light Reticle field size 20 mm × 15mm, 4 die per field 5:1 reduction lens Wafer Image exposure on wafer 1/5 of reticle field 4 mm × 3 mm, 4 die per exposure Serpentine stepping pattern The feature size directly depends on the wavelength of your lithographic system masks

P Type start wafer

Grow P-epitaxial layer

Spin Resist Coating

Expose N Well Mask

Develop resist (remove resist exposed to light)

Implant N Well

Remove Resist

Main 5-6 Steps: SEDAR (possible pre-spin action, e.g., deposit) Spin resist Expose (using mask) Develop resist ACTION (e.g., implant, etch, oxidize) Remove Resist

Anneal wafer to grow new oxide layer and diffuses N well

Remove oxide from anneal

Spin Resist

Develop resist

Expose resist with active diffusion mask

Grow oxide on exposed surface

Remove resist

Grown thin oxide over silicon surfaces

Deposit poly using Chemical Vapor Deposition (CVD)

Spin resist – expose resist using the GATE mask – develop resist – etch poly

Remove thin oxide layer where exposed

Spin resist – expose with P implant mask – develop resist – implant P

Spin resist – expose with N implant mask – develop resist – implant N

Remove resist – anneal wafer – oxide etch

Deposit oxide using CVD – spin resist – expose Contact mask – develop resist - etch contact hole – remove resist

Deposit metal 1 – spin resist - expose metal 1 mask – develop resist - etch metal – remove resist

Fabrication Summary Oxidation (Field oxide) Silicon substrate Silicon dioxide oxygen Photoresist Develop oxide Photoresist Coating photoresist Mask-Wafer Alignment and Exposure Mask UV light Exposed Photoresist exposed photoresist exposed photoresist G SD Active Regions top nitride S D G silicon nitride Nitride Deposition Contact holes S D GG Contact Etch Ion Implantation resistresist ox D G Scanning ion beam S Metal Deposition and Etch drain S D GG Metal contacts Polysilicon Deposition polysilicon Silane gas Dopant gas Oxidation (Gate oxide) gate oxide oxygen Photoresist Remove oxide RF Power Ionized oxygen gas Oxide Etch photoresist oxide RF Power Ionized CF 4 gas Polysilicon Mask and Etch RF Power oxideoxide Ionized CCl 4 gas poly gate RF Power

Spin polyimide – spin resist – expose via 1 mask – etch via – remove resist

Deposit metal 2 – spin resist – expose metal 2 – etch metal – remove resist

Spin polymide – spin resist – expose via 2 mask – etch via – remove resist

Deposit metal 3 – spin resist – expose metal 3 mask – develop resist – etch metal – remove resist

Spin polyimide – spin resist – expose passivation mask – develop resist - etch poly – remove resist – deposit nitride – spin resist – expose passivation mask – etch nitride – remove resist

More metal layers?

The printer Illuminator optics Beam line Excimer laser (193 nm ArF ) Operator console 4:1 Reduction lens NA = 0.45 to  0.6 Wafer transport system Reticle stage Auto-alignment system Wafer stage Reticle library (SMIF pod interface)

Summary Today: –Reviewed fabrication process Next time: –How to print different gates?