Controllers-system for APS – CubeSat nano-satellite Instructor: Daniel Alkalay Students: Moshe Emmer & Meir Harar Technion – Israel Institute of Technology Department of Electrical Engineering High Speed Digital Systems Lab

2 APS Cubesat Bus Architecture SA I/F & Bat C/D- Control Battery Attitude System Sensors & actuators Magneto-meter מד שמש Rate Gyro מגנטו-טורקרים Engines Sensors Actuators Accurate Positioning System שעון אטומי APS & TLM TransCeiver Power Distribution Over-current control TLM TT+C Attitude Control On-Board Controllers uBlaze + pBlaze + State-Machines Power Control Telemetry S&AI/FS&AI/F Payload TLM

3 –Intro to xilinx FPGA technology and development system (E.D.K/ I.S.E) –Create mini project, which includes several cores, peripherals and different communication modules. From characterization presentation … AR : Redefining mini project – to serve main project’s interests: Mini Project goals: Create a design, using MicroBlaze soft processor, which will implement a communication protocol between system and external device (Hyper terminal on PC, for instance). Designing will be divided into two aspects: 1.Hardware – building system architecture using available busses, peripherals IP ’ s etc ’ 2.Software – implementing a small program, written in C, and translate it into MicroBlaze target using EDK (learning and searching existed functions)

4 Progress so far…. Introduction to the Cube-Sat system, understanding control system architecture Learning Xilinx FPGA architecture Diving inside Lab tools level – Using the “Spartan III” starter board, experiencing in VHDL-only design (no MB) and E.D.K. Since no pre requisites (micro processors) – Time was dedicated to understand microprocessor logic concepts in general and MicroBlaze architecture in particular. (elaborated straight ahead…) Implemented a logic only system using VHDL (No MicroBlaze) Starting to implement a simple controller using MicroBlaze core, buses and few periphrials

5 What’s next ? Mini Project implementation – continue and finish Enlarge our tool box - apart MicroBlaze, study PicoBlaze and F.S.M notions and practice Study how to coordinate few processors After receiving preliminary algorithms input from AE students – implementing them using all three tools (MicroBlaz, PicoBlaze and FSM)

6 MicroBlaze – Soft processor for FPGA MicroBlaze Core Block Diagram

MicroBlaze Features Highly configurable, includes the following: Thirty-two 32-bit general purpose registers 32-bit instruction word with three operands and two addressing modes 32-bit address bus Single issue pipeline, divided into three stages: Fetch Decode Execute

32 general purpose registers (R0-R31) Five special purpose registers: PC (Program Counter) – The 32-bit address of the execution instruction MSR (Machine Status Register) – Contains control and status bits for the processor EAR (Exception Address register) – Stores the full load/store address that caused the exception ESR (Exception Status Register) – Contains status bits for the processor FSR (Floating-point Status Register) – Contains status bits for the floating-point unit Registers

Memory Architecture Harvard memory architecture Each address space has a 32-bit range (up to 4GByte of instructions / data memory) The instruction and data memory ranges can be mapped to the same physical memory Data accesses must be aligned (word access on word boundaries, halfword on halfword boundaries) Instruction accesses must be word aligned

Busses - LMB LMB (Local Memory Bus) – Synchronous, used primarily to access on-chip block RAM – Simple protocol, ensures that local block RAM are accessed in a single clock cycle

Busses – OPB OPB (On-chip Peripheral Bus) – General purpose synchronous bus, designed for easy connection of on-chip peripheral devices – 32-bit data bus, dynamic bus sizing (byte, halfword or word) – Support for multiple OPB bus masters – Features (for example): General Purpose IO Timer / Counter Block Watchdog Timer / Timebase Interrupt Controller OPB arbiter JTAG UART (for debugging purposes)

General Purpose IO Simple peripheral, consisting of two registers and a multiplexer for reading register contents and the GPIO I/O signals The GPIO block diagram is shown here:

13 Microblaze_0 BRAM_0I-LMB CntrlD-LMB Cntrl UART RS232 Microblaze_1 BRAM_1I-LMB CntrlD-LMB Cntrl LEDs OPB I-LMB D-LMB I-LMB D-LMB OPB F.S.L

14 Schedule Week 12 : –Learn how the MicroBlaze communicates with an off-board peripheral (e.g. HyperTerminal) through the OPB. Week 13-14: –Build the MiniProject – A microcontroller which implements a simple calculator using GPIO and HyperTerminal.