BIST AND DATA COMPRESSION 1 JTAG COURSE spring 2006 Andrei Otcheretianski

BIST AND DATA COMPRESSION2 Contents: BIST overview What is data compression? Data compression techniques  Ones-count  Transition-count  Parity check  Syndrome  LFSR

BIST AND DATA COMPRESSION3 Intro to BIST Built-In-Self-Test BIST is a capability of a circuit to test itself On-chip circuitry is used to apply a predetermined set of vectors to the CUT or DUT (circuit/device under test) Another on-chip circuit monitors the results of the test and checks them against the stored correct response.

BIST AND DATA COMPRESSION4 Generalized BIST architecture Test pattern generator CUT Data compression unit Comparator BIST controller Input test Sequence T Output Response R’ Signature S(R’) Correct signature S(R) Pass/Fail Indicator

BIST AND DATA COMPRESSION5 Data Compression The compression of large quantity of test response data into a compact set of fault signatures Consider a 64 bit circuit, test vectors, 16 bit signature sequences mapped to 2 16 signatures / 2 16 sequences produce the same signature on the average (aliases)

BIST AND DATA COMPRESSION6 Compression techniques: ONES-COUNT Assume single output circuit and output sequence R = r 1, r 2 … r m for m input vectors ONES-COUNT: count the total number of 1s in R

BIST AND DATA COMPRESSION7 ONES-COUNT (cont.) Aliasing (Error Masking): s-a-0 s-a = R = R = R 2

BIST AND DATA COMPRESSION8 Compression techniques: TRANSITION-COUNT Signature is the number of 0-to-1 and 1-to-0 transitions in the output data stream N D = R = R = R 0 counter TC(R 0 ) = 1 TC(R 1 ) = 1 (undetected) TC(R 2 ) = 0 D Q D clock

BIST AND DATA COMPRESSION9 TRANSITION-COUNT (cont.) The formula: Masking Probability:

BIST AND DATA COMPRESSION10 Compression Techniques PARITY CHECK Signature is the parity of circuit response: 0 if oven and 1 if odd. Masking Probability: Detects all faults with an odd number of error bits in the response. N D = R = R = R 0 p(R 0 ) = 1 p(R 1 ) = 0 p(R 2 ) = 0 D Q D clock

BIST AND DATA COMPRESSION11 Syndrome Testing Relies on exhaustive testing i.e. applying all 2 n vectors to an n input combinational circuit. Assume single output circuit. Syndrome is the normalized number of 1’s in the result. S = K / 2 n where K is total number of 1’s For example: Syndrome of AND gate is 1/8 and of OR gate is 7/8. Theorem: Any function F can be realized in such way that all single stuck-at faults will be syndrome detectable.

BIST AND DATA COMPRESSION12 For large n we should compute syndromes recursively. Assume X and Y are disjoint. Syndrome S 3 depends on C gate type. Proof: IF C = OR gate then K = K 1 2 n 2 + K 2 2 n 1 – K 1 K 2 S = K / 2 n = S 1 +S 2 -S 1 S 2 Computing Syndromes C1 C2 C S1S1 S2S2 S3S3 X Y Gate Type for CSyndrome S 3 ORS 1 +S 2 -S 1 S 2 ANDS1S2S1S2 NAND1-S 1 S 2 NOR1-(S 1 +S 2 -S 1 S 2 ) XORS 1 +S 2 -2S 1 S 2

BIST AND DATA COMPRESSION13 LFSR Linear Feedback Shift Register Shift register that feed back bits through XOR functions. Used both for Pseudo-Random Binary Sequence (PRBS) generation and for signature generation. By correctly choosing the points at which we take the feedback from an n -bit shift register, we can produce a PRBS of length 2 n – 1. This 3-bit LFSR produces A repeating string of 7 pseudo-random binary numbers

BIST AND DATA COMPRESSION14 Signature Analysis LFSR can be simply transformed into SISR (Serial-Input Signature Register) by adding an additional XOR gate This will perform data compression on the input sequence At the end of the sequence SISR will form a signature If the input sequence and SISR are long enough it is unlikely that two different sequences will produce the same signature. 3-bit SISR using LFSR

BIST AND DATA COMPRESSION15 LFSR: Masking Probability Let LFSR be of length n and bit stream of length m It can be shown that LFSR distributes ALL possible input streams equally over all signatures. Streams with the same signature: 2 m / 2 n Therefore: Masking Probability = 2 m-n / 2 m = 2 -n If all error streams are equally likely (ideal case) Depends only on register length!

BIST AND DATA COMPRESSION16 MISR SISR can only be used to test logic with a single output Solution: Multiple-Input Signature Register If we have n-bit long register we can accommodate up to n inputs to form the signature

BIST AND DATA COMPRESSION 17 THE END Thank you for listening…