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Built-In Self Test (BIST).  1. Introduction  2. Pattern Generation  3. Signature Analysis  4. BIST Architectures  5. Summary Outline.

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Presentation on theme: "Built-In Self Test (BIST).  1. Introduction  2. Pattern Generation  3. Signature Analysis  4. BIST Architectures  5. Summary Outline."— Presentation transcript:

1 Built-In Self Test (BIST)

2  1. Introduction  2. Pattern Generation  3. Signature Analysis  4. BIST Architectures  5. Summary Outline

3 Built-In Self Test (BIST)   1. Introduction  2. Pattern Generation  3. Signature Analysis  4. BIST Architectures  5. Summary

4 Built-In Self Test (BIST) 1. Introduction

5 Built-In Self Test (BIST) 1. Introduction General Structure

6 Built-In Self Test (BIST) General Structure Unit Under Test Data Compressor Data Generator Comparator Display Reference BIST Controller Start/StopReady Electronic System 1. Introduction

7 Built-In Self Test (BIST) 1. Introduction

8 Built-In Self Test (BIST) 1. Introduction

9 Built-In Self Test (BIST) 1. Introduction

10 Built-In Self Test (BIST)   1. Introduction  2. Pattern Generation  3. Signature Analysis  4. BIST Architectures  5. Summary

11 Built-In Self Test (BIST) 2. Pattern Generation

12 Built-In Self Test (BIST) 2. Pattern Generation

13 Built-In Self Test (BIST) 2. Pattern Generation

14 Built-In Self Test (BIST) 2. Pattern Generation

15 Built-In Self Test (BIST) 2. Pattern Generation A fixed set of “optimal” test patterns, usually derived from fault simulation, is used.

16 Built-In Self Test (BIST) 2. Pattern Generation

17 Built-In Self Test (BIST) 2. Pattern Generation

18 Built-In Self Test (BIST) 2. Pattern Generation

19 Built-In Self Test (BIST) 2. Pattern Generation

20 Built-In Self Test (BIST) Pseudo-Random Generation using LFSR 2. Pattern Generation

21 Built-In Self Test (BIST) Example of a 4-bit LFSR as a Pattern Generator. Pseudorandom states generated by the LFSR. Pseudo-Random Generation using LFSR 2. Pattern Generation

22 Built-In Self Test (BIST)   1. Introduction  2. Pattern Generation  3. Signature Analysis  4. BIST Architectures  5. Summary

23 3. Signature Analysis Built-In Self Test (BIST)

24 3. Signature Analysis Built-In Self Test (BIST) Methods for Response Evaluation Steps for Response Evaluation: 1 2 3 

25 r-Bit (Internal XOR) Signature Generator. The content of the LFSR is the remainder of the division operation. 3. Signature Analysis Serial Built-In Self Test (BIST)

26 r-Bit (External XOR) Signature Generator. The content of the LFSR is not the remainder of the division operation. Serial 3. Signature Analysis

27 Serial Example of a 4-bit (External) Signature Generator. Built-In Self Test (BIST) 3. Signature Analysis

28 r-Bit (Internal XOR) Parallel Signature Generator. r-Bit (External XOR) Parallel Signature Generator. Parallel Built-In Self Test (BIST) 3. Signature Analysis

29 Problem: fault masking When compacting results, there is a probability of fault masking ! Probability of failing to detect an error in the response sequence: Serial input Parallel input Where: K: length of the sequence (# of bits) r: length of the LFRS (# of bits) 2 mL- r – 1 2 mL – 1 2 k-r – 1 2 k – 1 Where: L: length of the sequence (# of test vectors) m: length of a vector (# of bits) r: length of the LFRS (# of bits) Built-In Self Test (BIST) 3. Signature Analysis

30 Built-In Self Test (BIST) 3. Signature Analysis Modular LFSR Serial Compacter Example

31 Built-In Self Test (BIST) 3. Signature Analysis Modular LFSR Parallel Compacter Example

32 Built-In Self Test (BIST)   1. Introduction  2. Pattern Generation  3. Signature Analysis  4. BIST Architectures  5. Summary

33 Built-In Self Test (BIST) 4. BIST Architectures Built-In Logic Block Observer (BILBO)

34 4. BIST Architectures Built-In Self Test (BIST)

35 Modular Bus-Oriented Design with “BILBO”. Built-In Self Test (BIST) 4. BIST Architectures Built-In Logic Block Observer (BILBO)

36 4. BIST Architectures Built-In Self Test (BIST)

37 4. BIST Architectures General Form of a BILBO B1 = 1, B2 = 1: S.A. B1 = 1, B2 = 0: Normal Op. B1 = 0, B2 = 0: Scan B1 = 0, B2 = 1: P.G. MUX: B2 = 1: Out = Q1. B2 = 0: Out = Sin.

38 Example: 8-bit-Length Datapath Built-In Self Test (BIST) 4. BIST Architectures B1 = 1, B2 = 0: S.A. B1 = 1, B2 = 1: Normal Op. B1 = 0, B2 = 0: Scan B1 = 0, B2 = 1: Not Ap. MUX: B1 = 1: Out = Q1. B1 = 0: Out = Sin.

39 Built-In Self Test (BIST) Example: 8-bit-Length Datapath 4. BIST Architectures

40 Built-In Self Test (BIST) Example: 8-bit-Length Datapath 4. BIST Architectures

41 Built-In Self Test (BIST)   1. Introduction  2. Pattern Generation  3. Signature Analysis  4. BIST Architectures  5. Summary

42 Built-In Self Test (BIST)


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