4. Test pattern generator is BIST scan chains TESTGENERATOR COMPACOMPACCTTOORRCOMPACOMPACCTTOORRCTOR Control

5. Generators  Capable of generating “good” pseudorandom test patterns Long aperiodic sequences No structural dependencies Low linear dependencies  Capable of driving large number of scan chains  Very simple hardware, small area  Fast operational speed  Easy to synthesize and analyze

6. Linear feedback shift registers  A series connection of delay elements (D flip-flops)  All feedback provided by means of XOR gates  The characteristic polynomial: x 16 + x 10 + x 7 + x 4 + 1  Two implementations Larger fanout but smaller delay 1514131211109876543210 0123456789101112131415

7. Checking Primitive polynomial 1000 An n-bit LFSR with nonzero seed generates m-sequence (maximum length sequence) with period 2 n -1 1 3 7 15 14 13 10 5 11 6 12 9 2 4 8 1 3 7 15 14 13 10 5 11 6 12 9 2 4 8 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 Absolute Primes

8. Properties of m-sequence  It consists of 2 n-1 1s and (2 n-1 - 1) 0s  There is one pattern of n consecutive 1s and one pattern of n - 1 consecutive 0s  Any pair comprising an m-sequence and its circularly shifted version is identical in 2 n-1 - 1 positions and differ in 2 n-1 positions  A sum of an m-sequence and its circularly shifted version is another shifted version of that m-sequence 000100110101111 001101011110001 011110001001101 Shifted by 8 bits Shifted by 2 bits

9. Linear dependencies a  d a  c  d a  b  c  d b  c  d a  b  c b  d a  c a  b  d c  d b  c a  b d c b a Cannot generate test 111 ! 1 1 0 1 0 1 0 1 1 0 0 0 Only these 4 combinations are possible dcba !

10. Probability of linear dependency  Gaussian elimination can be used to determine linear dependencies  Probability of k-bit linear dependency in m- sequence generated by an n-bit LFSR with primitive polynomial v For smaller sequences the probability may be much higher v Trinomials are particularly sensitive     1 0 1 2 22 1),( k i n in i knp

11. Probability of linear dependency k n = 30... 2 n - 1 n LFSR

12. Selection of polynomial  Degree: Large enough so the states will not repeat Large enough so the states will not repeat Large enough to reduce linear dependencies Large enough to reduce linear dependencies  Type Primitive Primitive Avoid trinomials (increased linear dependencies) Avoid trinomials (increased linear dependencies) Use at least pentanomials or septanomials Use at least pentanomials or septanomials  Seed value Selected through fault simulation Selected through fault simulation Selected intelligently through reseeding Selected intelligently through reseeding

13. Two-dimensional generators Structuraldependencies 0 1 2 3 4 5 6 7 8 9 10 11......

14. Two-dimensional generators PHASESHIFTERPHASESHIFTER 0 1 2 3 4 5 6 7 8 9 10 11 Find XOR network which guarantees minimum channel separation

15. XOR taps selection  Determine a dual LFSR  Initialize it to 10... 0 pattern  Run it for 2 n - 1 - k cycles  Read the resulting content of the dual LFSR Locations of 1s point out positions that should be included in a phase shifter to obtain a sequence shifted by k bits !

16. Application of LFSR duality 1000 1000 1 0 0 1 1 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 Shift 5 6 7 8 9101112131 DualDual

17. PRPG with phase shifter 0 1 2 3 4 5 6 7 8 9 10 11......

18. theoretical limit scan size Impact on linear dependency 16-bit type I LFRS 13 polynomials 15 specified bits No PS scan: 16  50 separation theoretical limit With PS

19. Extra fault coverage No phase shifter With phase shifters 54 polynomials, 16-, 24- and 32-bit type I LFRSs 0  the lowest fault coverage recorded maxavg.min

20. Cellular automata 1101010100  Capable of generating m-sequences with primitive polynomials  Improved modularity (compared to LFSRs)  Reduced need for phase shifters  May exhibit some structural dependencies

21. LFSRs External feedback LFSR Internal feedback LFSR - many levels of logic - many levels of logic - big fan-out - big fan-out

22. - large gate count - large gate count Hybrid LFSR and cellular automaton Hybrid LFSR Cellular automaton - delay and fan-out

23. Ring architecture   One sources per one destination   Fast 1 + x 4 + x 8 + x 12 + x 17 + x 20 + x 23 + x 28 + x 32 2828 2323 2020 1717 1212 8844   Modular PRPG

24. Synthesis 1 + x 12 + x 14 + x 27 + x 32 1514 13 1312 11 11691085437210 16171819202122232425262728293031 10 22 10 +12 = 22 10 +12 = 22 (32-12)/2 = 10 (32-12)/2 = 10 9 23 9 +14 = 23 9 +14 = 23 (32-14)/2 = 9 (32-14)/2 = 9 2 29 2 +27 = 29 2 +27 = 29 (32-27)/2 = 2 (32-27)/2 = 2

25. Comparison summary H LFSR IF LFSR EF LFSR CARing 2 k + 1 (2, k +1) 232 log 2 k 1 (1, log 2 k) 21 kk 2n - 2 (k +1) / 2kkk (k +1) / 2  h(x) = x n + x i +... + x j + 1 k   only for some polynomialsFan-out Levels of logic XOR gates Modularity kk**(k +1) / 2******

26. Reseeding of LFSRs LFSRLFSR Scan chain SeedSeed Test cube Identification of random pattern resistant faults by fault simulation of pseudo- random patterns Final fault grading of the test vectors obtained from the seeds by fault simulation of decompressed patterns Generation of test cubes for random pattern resistant faults using ATPG with dynamic compression, targeting several faults and leaving many “don’t care” inputs Computation of seeds by solving systems of linear equations through Gaussian elimination

27. Weighted random patterns 0 1 2 3 4 5 6 7 8 9 10 11 The average number of patterns to detect s-a-0: Pseudo-random: 1/0.5 -9 = 512 Weighted PS: 1/(1 - 2 -7 ) -9  1.07

29. Placement of compactor scan chains TESTGENERATOR COMPACOMPACCTTOORRCOMPACOMPACCTTOORRCTOR

30. Requirements for Logic BIST Objective: reduce the volume of test data and still be able to determine if the response was correct   simple hardware and small area   tested as part of the embedded test circuitry   simple software   compute the signature at the speed of the test   perform logarithmic compaction of data   no aliasing No scheme meets all criteria, but some come close! Properties of ideal compactors:

31. Requirements for deterministic test  Dramatically reduce volume of output test data  Maintain high test quality  Minimize impact on design and flow  Provide in-production diagnosis

32. MotivationDecompressor 99.99%99.99% 99.99% XXXX > 1 - Diagnosis >100x Quality X tolerance

33. QualityDecompressor 99.99%99.99% 99.99% Quality

34. CompactionDecompressor > 1 - >100x

35. X tolerance Decompressor XXXX

36. MotivationDecompressor Diagnosis

37. Compaction schemes  Time compactors polynomial division - signature analysis arithmetic accumulation various forms of counting  Space compactors XOR trees  Finite memory compactors Convolutional compactors Block-based compactors

38. Error models and aliasing  Single-bit and burst errors  Equally likely errors  Stationary and non-stationary independent errors  Asymmetric errors Aliasing or error masking - signature obtained from a faulty circuit is the same as that of the fault-free circuit 012 3456789 1011 OK 0 Fault detected 1

39. LFSR and Markov model 010 011 110 101 001 100 111 111000 000 11 000 100 110 011 001 100 010 001 000 000100110011001100010001000

40. Transient

41. Aliasing probability  How likely is it that a fault will generate a signature identical to a fault-free signature?  The Markov chain representing the compaction performed by n-bit LFSR is irreducible, aperiodic, and its transition matrix is doubly stochastic. Thus the probability that it enters any state is provided that a steady state has been reached. provided that a steady state has been reached. For n = 20, p  10 -6 and n = 30, p  10 -9 For n = 20, p  10 -6 and n = 30, p  10 -9 2 -n

42. Multiple Input Signature Register  Parallel data acquisition from multiple scan chains  Multiple error injections  High compaction speed  Simple hardware  Parallel data acquisition from multiple scan chains  Multiple error injections  High compaction speed  Simple hardware 1514131211109876543210

43. Time compactors MISR – infinite memory compactor   Compaction ratios  10 8 x   Unable to handle unknown states   Multiple-pass complicated fault diagnosis

44. Space compactors   Smaller compaction than time compactors   Handling of unknown states XOR tree

45. Space compactors   Certain minimum number of outputs required   Improved diagnostic capabilities

46. Space compactors Balanced tree is preferable scan chains

47. Fault cancellation scan scan

48. Unknown states scan scan XX XX

49. Selective space compactors  Deterministic compaction control... decoder control scan scan scan scan

50. Convolutional compactor 10:1 Polynomials 3/6

51. Architecture of convolutional compactor... Injector network Injector network

52. Observable scan chains 201713245809201136 1255100164216 821365256 size size124816 6101620 103664100120 16105196340504560 32465900168429364400 2425348488414641968 28351676125221363056 outputs outputs 3/Mpolynomials3/Mpolynomials

53. Error masking

55. 0.00.00.00.00.0 Error masking - no X states 0.0 4 3 0.0 +  1 0.0 +  2 … Error multiplicity 2i+12i23456781 … Error time span 01234 … Compactor size 1632

56. Probability of 4-error masking 100x compaction 3/M polynomials Error time span = 0 1 output 1 output 2 outputs 2 outputs 4 outputs 4 outputs 8 outputs 8 outputs 16 outputs 16 outputs 32 outputs 32 outputs Compactor size

57. Unknown states X Single error detected in the presence of a single X state

58. Diagnostic resolution Errors identified by unique syndroms

59. Diagnostic resolution (%) M = 8M = 8M = 8M = 8 M = 12 M = 16 M = 20 M = 24 M = 28 M = 32 M = 40 Error multiplicity Same time injection

60. Convolutional MISR ……… ………… … … Diagnostic mode 0 1 Go / No go test

61. Example... Injector network Injector network 474 8 Unobserved37.28%Unobserved37.28% X  0.39% 2.5M gates 57K scan cells 2.5M gates 57K scan cells............

62. Distribution of X states...12 3 4 5 6 7 8 9 10 474 Majority of unknown values produced by small fraction of scan chains 501002575 D.2 (2.1%) 95.5

63. Selective convolutional compactor Convolutionalcompactor... Disabling of defective scan chains

64. Experimental results Gates Scan cells Scan chains Unknown states (%) No. outputs Design Design Compaction ratio Compactor size Unobserved cells (%) … … with scan masking (%) Maximum masked chains D.11.6M 45K 96 0.72 4 24 36 16.96 4.32 2 2.5M 57K 474 0.39 4 118.5 32 37.28 1.76 9D.22.7M 138K 457 0.09 4 114.3 32 8.51 5.12 6D.3

65. Conclusions New class of finite memory compaction schemes  Dramatic compaction of test responses (100x)  Flexible number of outputs (  1)  Good observability in presence of X states (  95%)  Direct diagnosis from compacted responses