1. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt1 Lecture 21alt BIST -- Built-In Self-Test (Alternative to Lectures 25, 26 and 27) n Definition of BIST n Pattern generator n LFSR n Response analyzer n MISR n Aliasing probability n BIST architectures n Test per scan n Test per clock n Circular self-test n Memory BIST n Summary

2. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt2 Define Built-In Self-Test n Implement the function of automatic test equipment (ATE) on circuit under test (CUT). n Hardware added to CUT: n Pattern generation (PG) n Response analysis (RA) n Test controller CUT Stored Test Patterns Stored responses Pin Electronics Comparator hardware Test control HW/SW ATE PG RA CUT Go/No-go signature Test control logic CK BIST Enable

3. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt3 Pattern Generator (PG) n RAM or ROM with stored deterministic patterns n Counter n Pseudorandom pattern generator n Feedback shift register n Cellular automata

4. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt4 Pseudorandom Integers 0 5 1 3 7 62 4 Start +3 Sequence: 2, 5, 0, 3, 6, 1, 4, 7, 2... 0 5 1 3 7 62 4 Start +2 Sequence: 2, 4, 6, 0, 2... X k = X k-1 + 3 (modulo 8)X k = X k-1 + 2 (modulo 8) Maximum length sequence: 3 and 8 are relative primes.

5. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt5 Pseudo-Random Pattern Generation n Standard Linear Feedback Shift Register (LFSR)  Produces patterns algorithmically – repeatable  Has most of desirable random # properties n May not cover all 2 n input combinations n Long sequences needed for good fault coverage eitherh i = 0, i.e., XOR is deleted orh i = X i Initial state (seed): X 0, X 1,..., X n-1 must not be 0, 0,..., 0

6. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt6 Matrix Equation for Standard LFSR X 0 (t + 1) X 1 (t + 1). X n-3 (t + 1) X n-2 (t + 1) X n-1 (t + 1) 10...00h110...00h1 01...00h201...00h2 00...00100...001 …… …………… ……… 0. 1 0 h n-2 0. 0 1 h n-1 X 0 (t) X 1 (t). X n-3 (t) X n-2 (t) X n-1 (t) = X (t + 1) = T s X (t) (T s is companion matrix)

7. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt7 LFSR Implements a Galois Field  Galois field (mathematical system):  Multiplication by X same as right shift of LFSR  Addition operator is XOR ( )  T s companion matrix:  1 st column 0, except nth element which is always 1 (X 0 always feeds back)  Rest of row n – feedback coefficients h i  Remaining identity matrix means a right shift n Near-exhaustive (maximal length) LFSR  Cycles through 2 n – 1 states (excluding all-0) 

8. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt8 LFSR Properties n Must not initialize to all 0’s – hangs n If X is initial state, LFSR progresses through states X, T s X, T s 2 X, T s 3 X, … n Matrix period: Smallest k such that T s k = I  k = LFSR cycle length  Maximum length k = 2 n -1, when feedback (characteristic) polynomial is primitive  Example: 1 + X+ X 3 n Characteristic polynomial: 1 + h 1 x + h 2 X 2 + … + h n-1 X n-1 + X n

9. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt9 LFSR: 1 + X + X 3 D Q X 2 D Q X 1 D Q X 0 X2X2 X1X1 X0X0 CK RESET 000 100001 110 010 111 101 011 RESET Test of primitiveness: Characteristic polynomial of degree n must divide 1 + X q for q = n, but not for q < n

10. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt10 LFSR as Response Analyzer n Use cyclic redundancy check code (CRCC) generator (LFSR) for response compacter n Treat data bits from circuit POs to be compacted as a decreasing order coefficient polynomial n CRCC divides the PO polynomial by its characteristic polynomial  Leaves remainder of division in LFSR  Must initialize LFSR to seed value (usually 0) before testing n After testing – compare signature in LFSR to precomputed signature of fault-free circuit

11. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt11 Example Modular LFSR Response Analyzer n LFSR seed is “00000”

12. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt12 Signature by Logic Simulation Input bits Initial State 1 0 1 0 1 0 X0010001111X0010001111 X1001000010X1001000010 X2000100001X2000100001 X3000010101X3000010101 X4000001010X4000001010 Signature

13. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt13 Signature by Polynomial Division X2X7X7X2X7X7 + 1 + X 5 X 5 + X 3 X 3 + X 2 + X + 1 X 5 + X 3 + X + 1 Char. polynomial remainder Input bit stream: 0 1 0 1 0 0 0 1 0 ∙ X 0 + 1 ∙ X 1 + 0 ∙ X 2 + 1 ∙ X 3 + 0 ∙ X 4 + 0 ∙ X 5 + 0 ∙ X 6 + 1 ∙ X 7 Signature: X 0 X 1 X 2 X 3 X 4 = 1 0 1 1 0

14. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt14 Multiple-Input Signature Register (MISR) n Problem with ordinary LFSR response compacter:  Too much hardware if one of these is put on each primary output (PO) n Solution: MISR – compacts all outputs into one LFSR  Works because LFSR is linear – obeys superposition principle  Superimpose all responses in one LFSR – final remainder is XOR sum of remainders of polynomial divisions of each PO by the characteristic polynomial

15. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt15 Modular MISR Example X 0 (t + 1) X 1 (t + 1) X 2 (t + 1) 001001 010010 110110 = X 0 (t) X 1 (t) X 2 (t) d 0 (t) d 1 (t) d 2 (t) +

16. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt16 Aliasing Probability n Aliasing means that faulty signature matches fault- free signature n Aliasing probability ~ 2 -n n where n = length of signature register n Example 1: n = 4, Aliasing probability = 6.25% n Example 2: n = 8, Aliasing probability = 0.39% n Example 3: n = 16, Aliasing probability = 0.0015% Fault-free signature 2 n -1 faulty signatures

17. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt17 BIST Architectures n Test per scan n Test per clock n Circular self-test n Memory BIST

18. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt18 Test Per Scan BIST Scan register Comb. logic Scan register Comb. logic Scan register Comb. logic PG RA BIST Control logic PI and PO disabled during test BIST enable Go/No-go signature

19. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt19 Test per Clock BIST n New fault set tested every clock period n Shortest possible pattern length  10 million BIST vectors, 200 MHz test / clock  Test Time = 10,000,000 / 200 x 10 6 = 0.05 s  Shorter fault simulation time than test / scan

20. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt20 Circular Self Test

21. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt21 Built-in Logic Block Observer (BILBO) n Combined functionality of D flip-flop, pattern generator, response analyzer, and scan chain  Reset all FFs to 0 by scanning in zeros

22. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt22 Test per Clock with BILBO n SI – Scan In n SO – Scan Out n Characteristic polynomial: 1 + x + … + x n n CUTs A and C: BILBO1 is MISR, BILBO2 is LFSR n CUT B: BILBO1 is LFSR, BILBO2 is MISR

23. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt23 BILBO Serial Scan Mode n B1 B2 = “00” n Dark lines show enabled data paths

24. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt24 BILBO LFSR Pattern Generator Mode n B1 B2 = “01”

25. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt25 BILBO in DFF (Normal) Mode n B1 B2 = “10”

26. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt26 BILBO in MISR Mode n B1 B2 = “11”

27. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt27 Memory BIST

28. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt28 Summary n LFSR pattern generator and MISR response analyzer – preferred BIST methods n BIST has overheads: test controller, extra circuit delay, primary input MUX, pattern generator, response compacter, DFT to initialize circuit and test the test hardware n BIST benefits:  At-speed testing for delay and stuck-at faults  Drastic ATE cost reduction  Field test capability  Faster diagnosis during system test  Less effort to design testing process  Shorter test application times