1. TOPIC : CBIST, CEBS UNIT 5 : BIST and BIST Architectures Module 5.2 Specific BIST Architectures

2. Concurrent BIST Architecture (CBIST) It has both the concepts of offline and online BIST. The circuit under test (CUT) must be combinational. BIST hardware is separate from the normal hardware. This technique can be employed to sequential circuits if partitioned into blocks of combinational logic that can be tested as separate entities. There is no requirement of boundary or internal scan paths. A centralized BIST architecture can be used to reduce the hardware overhead.

3. Contd … Concurrent BIST Architecture

4. Contd … Offline testing: In this case the PRPG drives the CUT and its output is compressed in MISR. Input to CUT is given from PRPG by choosing appropriate N/T signal. Online testing: PRPG and MISR are initialized and held in their initial state until enabled by EN signal. Normal inputs are applied to the CUT, when a match exist between the normal inputs and the state of PRPG, allowing the PRPG and MISR to advance to next stage.

5. Contd … MISR also samples the output and proceeds t next state. The same process is repeated whenever there is a match between the normal input and PRPG curent state. When the PRPG state reaches the pre-specified final state, the signature of the MISR is verified.

6. Centralized & Embedded BIST Architecture with Boundary Scan(CEBS) This is a version of LOCST architecture.

7. Contd … In input boundary scan register, the first ‘r’ bits act as PRPG/SRSG. In output boundary scan register, the last ‘s’ bits act as both MISR and SISR. A test mode is set and the scan registers are seeded. RPG loads the scan path with pseudorandom test data.

8. Contd … The scan-path registers are loaded in parallel with system data, except for signature register SR, which operates in MISR mode. The scan-path is again loaded with pseudorandom data while the signature register operates in SISR mode, compressing data that were in the scan path.