1. ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTEMS Built-In Self-Test (BIST) - 1

2. 10/22/20152 Overview: TPG and RC Motivation and economics Definitions Built-in self-testing (BIST) process BIST pattern generation (PG) BIST response compaction (RC) Aliasing definition and example Summary

3. 10/22/20153 BIST Motivation Useful for field test and diagnosis (less expensive than a local automatic test equipment) Software tests for field test and diagnosis:  Low hardware fault coverage  Low diagnostic resolution  Slow to operate Hardware BIST benefits:  Lower system test effort  Improved system maintenance and repair  Improved component repair  Better diagnosis at component level

4. 10/22/20154 Costly Test Problems Alleviated by BIST Increasing chip logic-to-pin ratio – harder observability Increasingly dense devices and faster clocks Increasing test generation and application times Increasing size of test vectors stored in ATE Expensive ATE needed for GHz clocking chips Hard testability insertion – designers unfamiliar with gate- level logic, since they design at behavioral level In-circuit testing no longer technically feasible Circuit testing cannot be easily partitioned

5. 10/22/20155 Design and test + / - Fabri- cation + Manuf. Test - Level Chips Boards System Maintenance test - Diagnosis and repair - Service interruption - + Cost increase - Cost saving +/- Cost increase may balance cost reduction Benefits and Costs of BIST with DFT

6. 10/22/20156 Economics – BIST Costs  Chip area overhead for: Test controller Hardware pattern generator Hardware response compacter Testing of BIST hardware  Pin overhead -- At least 1 pin needed to activate BIST operation  Performance overhead – extra path delays due to BIST  Yield loss – due to increased chip area or more chips In system because of BIST  Reliability reduction – due to increased area  Increased BIST hardware complexity – happens when BIST hardware is made testable

7. 10/22/20157 BIST Benefits Faults tested:  Single combinational / sequential stuck-at faults  Delay faults  Single stuck-at faults in BIST hardware BIST benefits  Reduced testing and maintenance cost  Lower test generation cost  Reduced storage / maintenance of test patterns  Simpler and less expensive ATE  Can test many units in parallel  Shorter test application times  Can test at functional system speed

8. 10/22/20158 Definitions BILBO – Built-in logic block observer, extra hardware added to flip-flops so they can be reconfigured as an LFSR pattern generator or response compacter, a scan chain, or as flip-flops Concurrent testing – Testing process that detects faults during normal system operation CUT – Circuit-under-test Exhaustive testing – Apply all possible 2 n patterns to a circuit with n inputs Irreducible polynomial – Boolean polynomial that cannot be factored LFSR – Linear feedback shift register, hardware that generates pseudo-random pattern sequence

9. 10/22/20159 More Definitions Primitive polynomial – Boolean polynomial p (x) that can be used to compute increasing powers n of x n modulo p (x) to obtain all possible non-zero polynomials of degree less than p (x) Pseudo-exhaustive testing – Break circuit into small, overlapping blocks and test each exhaustively Pseudo-random testing – Algorithmic pattern generator that produces a subset of all possible tests with most of the properties of randomly-generated patterns Signature – Any statistical circuit property distinguishing between bad and good circuits TPG – Hardware test pattern generator

10. 10/22/201510 BIST Process Test controller – Hardware that activates self-test simultaneously on all PCBs Each board controller activates parallel chip BIST Diagnosis effective only if very high fault coverage

11. 10/22/201511 BIST Architecture Note: BIST cannot test wires and transistors:  From PI pins to Input MUX  From POs to output pins

12. 10/22/201512 BILBO – Works as Both a TPG and a RC Built-in Logic Block Observer (BILBO) -- 4 modes: 1. Flip-flop 2. LFSR pattern generator 3. LFSR response compacter 4. Scan chain for flip-flops

13. 10/22/201513 Complex BIST Architecture Testing epoch I:  LFSR1 generates tests for CUT1 and CUT2  BILBO2 (LFSR3) compacts CUT1 (CUT2) Testing epoch II:  BILBO2 generates test patterns for CUT3  LFSR3 compacts CUT3 response

14. 10/22/201514 Bus-Based BIST Architecture Self-test control broadcasts patterns to each CUT over bus – parallel pattern generation Awaits bus transactions showing CUT’s responses to the patterns: serialized compaction

15. 10/22/201515 Pattern Generation Store in ROM – too expensive Exhaustive Pseudo-exhaustive Pseudo-random (LFSR) – Preferred method Binary counters – use more hardware than LFSR Modified counters Test pattern augmentation  LFSR combined with a few patterns in ROM  Hardware diffracter – generates pattern cluster in neighborhood of pattern stored in ROM

16. 10/22/201516 Exhaustive Pattern Generation (A Counter) Shows that every state and transition works For n-input circuits, requires all 2 n vectors Impractical for large n ( > 20 )

17. 10/22/201517 Pseudo-Exhaustive Pattern Generation

18. 10/22/201518 Random Pattern Testing Bottom: Random- Pattern Resistant circuit

19. 10/22/201519 Pseudo-Random Pattern Generation Standard Linear Feedback Shift Register (LFSR)  Normally known as External XOR type LFSR  Produces patterns algorithmically – repeatable  Has most of desirable random # properties Need not cover all 2 n input combinations Long sequences needed for good fault coverage

20. 10/22/201520 Theory: LFSRs  Galois field (mathematical system):  Multiplication by x same as right shift of LFSR  Addition operator is XOR (  )  T s companion matrix for a standard (external EOR type) LFSR:  1 st column 0, except nth element which is always 1 (X 0 always feeds X n-1 )  Rest of row n – feedback coefficients h i  Rest is identity matrix I – means a right shift Near-exhaustive (maximal length) LFSR  Cycles through 2 n – 1 states (excluding all-0)  1 pattern of n 1’s, one of n-1 consecutive 0’s 

21. 10/22/201521 Standard n-Stage LFSR If h i = 0, that XOR gate is deleted

22. 10/22/201522 Matrix Equation for Standard LFSR X 0 (t + 1) X 1 (t + 1). X n-3 (t + 1) X n-2 (t + 1) X n-1 (t + 1) 10...00h110...00h1 01...00h201...00h2 00...00100...001 …… …………… ……… 0. 1 0 h n-2 0. 0 1 h n-1 X 0 (t) X 1 (t). X n-3 (t) X n-2 (t) X n-1 (t) = X (t + 1) = T s X (t) (T s is companion matrix)

23. 10/22/201523 LFSR Theory (contd.) Cannot initialize to all 0’s – hangs If X is initial state, progresses through states X, T s X, T s 2 X, T s 3 X, … Matrix period: Smallest k such that T s k = I  k LFSR cycle length Described by characteristic polynomial: f (x) = |T s – I X | = 1 + h 1 x + h 2 x 2 + … + h n-1 x n-1 + x n 

24. 10/22/201524 Example External XOR LFSR

25. 10/22/201525 Example: External XOR LFSR (contd.) Matrix equation: Companion matrix: Characteristic polynomial: –f (x) = 1 + x + x 3 (read taps from right to left) Always have 1 and x n terms in polynomial X 0 (t + 1) X 1 (t + 1) X 2 (t + 1) 001001 101101 010010 X 0 (t) X 1 (t) X 2 (t) = TSTS 001001 101101 010010 =

26. 10/22/201526 External XOR LFSR Pattern sequence for example LFSR (earlier): Never repeat an LFSR pattern more than 1 time –Repeats same error vector, cancels fault effect X0X1X2X0X1X2 100100 001001 010010 101101 011011 111111 110110 100100 001001 …

27. 10/22/201527 Generic Modular (Internal XOR) LFSR

28. 10/22/201528 Modular Internal XOR LFSR Described by companion matrix T m = T s T Internal XOR LFSR – XOR gates in between D flip-flops Equivalent to standard External XOR LFSR  With a different state assignment  Faster – usually does not matter  Same amount of hardware X (t + 1) = T m x X (t) f (x) = | T m – I X | = 1 + h 1 x + h 2 x 2 + … + h n-1 x n-1 + x n Right shift – equivalent to multiplying by x, and then dividing by characteristic polynomial and storing the remainder

29. 10/22/201529 Modular LFSR Matrix X 0 (t + 1) X 1 (t + 1) X 2 (t + 1). X n-3 (t + 1) X n-2 (t + 1) X n-1 (t + 1) 001...000001...000 000...010000...010 010...000010...000 ……… ……………… ……… 000...001000...001 1 h 1 h 2. h n-3 h n-2 h n-1 X 0 (t) X 1 (t) X 2 (t). X n-3 (t) X n-2 (t) X n-1 (t) = 000...000000...000

30. 10/22/201530 Example Modular LFSR f (x) = 1 + x 2 + x 7 + x 8 Read LFSR tap coefficients from left to right

31. 10/22/201531 Primitive Polynomials Want LFSR to generate all possible 2 n – 1 patterns (except the all-0 pattern) Conditions for this – must have a primitive polynomial:  Monic – coefficient of x n term must be 1 Modular LFSR – all D FF’s must right shift through XOR’s from X 0 through X 1, …, through X n-1, which must feed back directly to X 0 Standard LFSR – all D FF’s must right shift directly from X n-1 through X n-2, …, through X 0, which must feed back into X n-1 through XORing feedback network

32. 10/22/201532  Characteristic polynomial must divide the polynomial 1 + x k for k = 2 n – 1, but not for any smaller k value  See Appendix B of book for tables of primitive polynomials  Following is related to aliasing: –If p (error) = 0.5, no difference between behavior of primitive & non-primitive polynomial –But p (error) is rarely = 0.5 In that case, non- primitive polynomial LFSR takes much longer to stabilize with random properties than primitive polynomial LFSR Primitive Polynomials (continued)

33. 10/22/201533 Weighted Pseudo-Random Pattern Generation If p (1) at all PIs is 0.5, p F (1) = 0.5 8 = Will need enormous # of random patterns to test a stuck-at 0 fault on F -- LFSR p (1) = 0.5  We must not use an ordinary LFSR to test this IBM – holds patents on weighted pseudo-random pattern generator in ATE 1 256 255 256 1 256 p F (0) = 1 – = F s-a-0

34. 10/22/201534 Weighted Pseudo-Random Pattern Generator LFSR p (1) = 0.5 Solution: Add programmable weight selection and complement LFSR bits to get p (1)’s other than 0.5 Need 2-3 weight sets for a typical circuit Weighted pattern generator drastically shortens pattern length for pseudo-random patterns

35. 10/22/201535 Weighted Pattern Gen. w10000w10000 w20011w20011 Inv. 0 1 0 1 p (output) ½ ¼ 3/4 w11111w11111 w20011w20011 p (output) 1/8 7/8 1/16 15/16 Inv. 0 1 0 1

36. 10/22/201536 Test Pattern Augmentation Secondary ROM – to get LFSR to 100% SAF coverage  Add a small ROM with missing test patterns  Add extra circuit mode to Input MUX – shift to ROM patterns after LFSR done  Important to compact extra test patterns Use diffracter:  Generates cluster of patterns in neighborhood of stored ROM pattern Transform LFSR patterns into new vector set Put LFSR and transformation hardware in full- scan chain

37. 10/22/201537 Response Compaction Severe amounts of data in CUT response to LFSR patterns – example:  Generate 5 million random patterns  CUT has 200 outputs  Leads to: 5 million x 200 = 1 billion bits response Uneconomical to store and check all of these responses on chip Responses must be compacted

38. 10/22/201538 Definitions Aliasing – Due to information loss, signatures of good and some bad machines match Compaction – Drastically reduce # bits in original circuit response – lose information Compression – Reduce # bits in original circuit response – no information loss – fully invertible (can get back original response) Signature analysis – Compact good machine response into good machine signature. Actual signature generated during testing, and compared with good machine signature Transition Count Response Compaction – Count # transitions from 0 1 and 1 0 as a signature

39. 10/22/201539 Transition Counting

40. 10/22/201540 Transition Counting Details n Transition count: C (R) =  (r i r i-1 ) for all m primary outputs n To maximize fault coverage:  Make C (R0) – good machine transition count – as large or as small as possible i = 1 m 

41. 10/22/201541 LFSR for Response Compaction Use cyclic redundancy check code (CRCC) generator (LFSR) for response compacter Treat data bits from circuit POs to be compacted as a decreasing order coefficient polynomial CRCC divides the PO polynomial by its characteristic polynomial  Leaves remainder of division in LFSR  Must initialize LFSR to seed value (usually 0) before testing After testing – compare signature in LFSR to known good machine signature Critical: Must compute good machine signature

42. 10/22/201542 Example Modular LFSR Response Compacter LFSR seed value is “00000”

43. 10/22/201543 Polynomial Division Logic simulation: Remainder = 1 + x 2 + x 3 0 1 0 1 0 0 0 1 0 x 0 + 1 x 1 + 0 x 2 + 1 x 3 + 0 x 4 + 0 x 5 + 0 x 6 + 1 x 7 Inputs Initial State 1 0 1 0 1 0 X0010001111X0010001111 X1001000010X1001000010 X2000100001X2000100001 X3000010101X3000010101 X4000001010X4000001010........ Logic Simulation:

44. 10/22/201544 Symbolic Polynomial Division x2x7x7x2x7x7 + 1 + x 5 x 5 + x 3 x 3 + x 2 + x + 1 x 5 + x 3 + x + 1 remainder Remainder matches that from logic simulation of the response compacter!

45. 10/22/201545 Multiple-Input Signature Register (MISR) Problem with ordinary LFSR response compacter:  Too much hardware if one of these is put on each primary output (PO) Solution: MISR – compacts all outputs into one LFSR  Works because LFSR is linear – obeys superposition principle  Superimpose all responses in one LFSR – final remainder is XOR sum of remainders of polynomial divisions of each PO by the characteristic polynomial

46. 10/22/201546 MISR Matrix Equation d i (t) – output response on PO i at time t X 0 (t + 1) X 1 (t + 1). X n-3 (t + 1) X n-2 (t + 1) X n-1 (t + 1) 10...00h110...00h1 00...00100...001 …… …………… ……… 0. 1 0 h n-2 0. 0 1 h n-1 X 0 (t) X 1 (t). X n-3 (t) X n-2 (t) X n-1 (t) = d 0 (t) d 1 (t). d n-3 (t) d n-2 (t) d n-1 (t) +

47. 10/22/201547 Modular MISR Example X 0 (t + 1) X 1 (t + 1) X 2 (t + 1) 001001 010010 110110 = X 0 (t) X 1 (t) X 2 (t) d 0 (t) d 1 (t) d 2 (t) +

48. 10/22/201548 Multiple Signature Checking Use 2 different testing epochs:  1 st with MISR with 1 polynomial  2 nd with MISR with different polynomial Reduces probability of aliasing –  Very unlikely that both polynomials will alias for the same fault Low hardware cost:  A few XOR gates for the 2 nd MISR polynomial  A 2-1 MUX to select between two feedback polynomials

49. 10/22/201549 Aliasing Probability Aliasing – when bad machine signature equals good machine signature Consider error vector e (n) at POs  Set to a 1 when good and faulty machines differ at the PO at time t P al aliasing probability p probability of 1 in e (n) Aliasing limits:  0 < p ½, p k P al (1 – p) k  ½ p 1, (1 – p) k P al p k         

50. 10/22/201550 Aliasing Probability Graph

51. 10/22/201551 Experiment Hardware n 3 bit exhaustive binary counter for pattern generator

52. 10/22/201552 Transition Counting vs. LFSR LFSR aliases for f sa1, transition counter for a sa1 Pattern abc 000 001 010 011 100 101 110 111 Transition Count LFSR Good 0 1 0 1 3 001 a sa1 0 1 0 1 Signatures 3 101 f sa1 1 0 001 b sa1 0 1 010 Responses

53. 10/22/201553 Summary LFSR pattern generator and MISR response compacter – preferred BIST methods BIST has overheads: test controller, extra circuit delay, Input MUX, pattern generator, response compacter, DFT to initialize circuit & test the test hardware BIST benefits:  At-speed testing for delay & stuck-at faults  Drastic ATE cost reduction  Field test capability  Faster diagnosis during system test  Less effort to design testing process  Shorter test application times

54. 10/22/201554 Appendix

55. 10/22/201555 LFSR Fault Coverage Projection Fault detection probability by a random number p (x) dx = fraction of detectable faults with detection probability between x and x + dx  p (x) dx 0 when 0 x 1  p (x) dx = 1 Exist p (x) dx faults with detection probability x Mean coverage of those faults is x p (x) dx Mean fault coverage y n of 1 st n vectors: I (n) = 1 - (1 – x) n p (x) dx y n 1 – I (n) + (15.6) n total faults    0 1  0 1  

56. 10/22/201556 LFSR Fault Coverage & Vector Length Estimation Random-fault-detection (RFD) variable:  Vector # at which fault first detected  w i # faults with RFD variable i So p (x) =  w i p i (x) n s size of sample simulated; N # test vectors w 0 n s -  w i Method:  Estimate random first detect variables w i from fault simulator using fault sampling  Estimate I (n) using book Equation 15.8  Obtain test length by inverting Equation 15.6 & solving numerically i = 1 N    N 1ns1ns 

57. 10/22/201557 Additional MISR Aliasing n MISR has more aliasing than LFSR on single PO  Error in CUT output d j at t i, followed by error in output d j+h at t i+h, eliminates any signature error if no feedback tap in MISR between bits Q j and Q j+h.

58. 10/22/201558 Aliasing Theorems Theorem 15.1: Assuming that each circuit PO d ij has probability p of being in error, and that all outputs d ij are independent, in a k-bit MISR, P al = 1/(2 k ), regardless of initial condition of MISR. Not exactly true – true in practice. Theorem 15.2: Assuming that each PO d ij has probability p j of being in error, where the p j probabilities are independent, and that all outputs d ij are independent, in a k-bit MISR, P al = 1/(2 k ), regardless of the initial condition.