© Electronics Recall Last Lecture The MOSFET has only one current, I D Operation of MOSFET – NMOS and PMOS – For NMOS, V GS > V TN V DS sat = V GS – V TN – For PMOS V SG > |V TP | V SD sat = V SG + V TP
© Electronics I D versus V DS (NMOS) or I D versus V SD (PMOS)
© Electronics NMOS o V TN is POSITIVE o V GS > V TN to turn on o Triode/non-saturation region o Saturation region o V DSsat = V GS - V TN PMOS o V TP is NEGATIVE o V SG > |V TP | to turn on o Triode/non-saturation region o Saturation region o V SDsat = V SG + V TP
© Electronics DC analysis of FET
© Electronics MOSFET DC Circuit Analysis MOSFET DC Circuit Analysis - NMOS The source terminal is at ground and common to both input and output portions of the circuit. The C C acts as an open circuit to dc but it allows the signal voltage to the gate of the MOSFET. In the DC equivalent circuit, the gate current into the transistor is zero, the voltage at the gate is given by a voltage divider principle: V G = V TH = R 2 V DD R 1 + R 2 Use KVL at GS loop: V GS –V TH + 0 = 0 V GS = V TH
© Electronics MOSFET DC Circuit Analysis - NMOS 2.Assume the transistor is biased in the saturation region, the drain current: 3.Use KVL at DS loop I D R D + V DS – V DD = 0 4.Calculate V DSsat = V GS - V TN 1.Calculate the value of V GS 5.Confirm your assumption: If V DS > V DS (sat) = V GS – V TN, then the transistor is biased in the saturation region. If V DS < V DS (sat), then the transistor is biased in the non-saturation region.
© Electronics Calculate the drain current and drain to source voltage of a common source circuit with an n-channel enhancement mode MOSFET. Assume that R 1 = 30 k , R 2 = 20 k , R D = 20 k , V DD = 5V, V TN = 1V and K n = 0.1 mA/V 2 V DSsat = V GS – V TN = 2 – 1 = 1V, so, V DS > V DSsat, our assumption that the transistor is in saturation region is correct V TH = 20 5 = 2V hence V GS = V TH = 2V EXAMPLE:
© Electronics EXAMPLE The transistor has parameters V TN = 2V and K n = 0.25mA/V 2. Find I D and V DS V DD = 10V R D = 10k R 1 = 280k R 2 = 160k
© Electronics Solution 2. Assume in saturation mode: I D = K n (V GS - V TN ) 2 So, I D = mA 3. KVL at DS loop: V DS = V DD – I D R D = 10 – (10) = 3.31 V 4. V DS sat = V GS – V TN = – 2 = V So, V DS > V DSsat, therefore, assumption is correct! 1. V TH = = V Answer: I D = mA and V DS = 3.31 V KVL at GS loop: V GS – V TH + 0 = 0 V GS = V TH
© Electronics MOSFET DC Circuit Analysis MOSFET DC Circuit Analysis - PMOS Different notation: V SG and V SD Threshold Voltage = V TP Use KVL at GS loop: V SG V TH – V DD = 0 V SG = V DD - V TH V G = V TH = R 2 V DD R 1 + R 2
© Electronics MOSFET DC Circuit Analysis MOSFET DC Circuit Analysis - PMOS Assume the transistor is biased in the saturation region, the drain current: Calculate V SD : Use KVL at DS loop: V SD + I D R D - V DD = 0 If V SD > V SD (sat) = V SG + V TP, then the transistor is biased in the saturation region. If V SD < V SD (sat), then the transistor is biased in the non-saturation region. V SD = V DD - I D R D I D = K p (V SG + V TP ) 2
© Electronics 50 k 7.5 k Calculate the drain current and source to drain voltage of a common source circuit with an p-channel enhancement mode MOSFET. Also find the power dissipation. Assume that, V TP = -1.1V and K p = 0.3 mA/V 2 Use KVL at SG loop: V SG – 5 = 0 V SG = 5 – 2.5 = 2.5 V Assume biased in saturation mode: Hence, I D = 0.3 ( 2.5 – 1.1) 2 = mA Calculate V SD Use KVL at SD loop: V SD + I D R D – 5 = 0 V SD = 5 - I D R D V SD = 5 – ( 7.5) = V 5V V SG > |V TP |
© Electronics V SD sat = V SG + V TP = 2.5 – 1.1 = 1.4V Hence, V SD < V SD sat. Therefore assumption is incorrect. The transistor is in non-saturation mode! I D = ( 2.5 – 1.1) (5 – I D R D ) – (5 – I D R D ) 2 I D = (5 – 7.5I D ) – (5-7.5I D ) 2 I D = – 21I D – (25 – 75I D I D 2 ) I D = – 21I D I D – 56.25I D I D 2 – I D + 11 = 0 I D = mA I D = mA
© Electronics I D = mAI D = mA V SD = 5 – I D R D = 0.98 V V SD = 5 – I D R D = 2.26 V V SD sat = V SG + V TP = 2.5 – 1.1 = 1.4V 2.26V > 1.4V Bigger than V SD sat : not OK 0.98V < 1.4V Smaller than V SD sat : OK! Answer: I D = mA and V SD = 0.98V Power dissipation = I D x V SD = mW
© Electronics LOAD LINE Common source configuration i.e source is grounded. It is the linear equation of I D versus V DS Use KVL V DS = V DD – I D R D I D = -V DS + V DD RDRD RDRD
© Electronics I D (mA) V DS (V) V GS V DS IDID Q-POINTS y-intercept x-intercept
© Electronics DC Analysis where source is NOT GROUNDED For the NMOS transistor in the circuit below, the parameters are V TN = 1V and K n = 0.5 mA/V 2.
© Electronics 1. G et an expression for V GS in terms of I D use KVL: 0 + V GS + 1(I D ) = 0 V GS = 4 - I D 2. Assume in saturation I D = 0.5 ( 4 - I D – 1) 2 = 0.5 ( 3 – I D ) 2 2I D = 9 – 6I D + I D 2 I D 2 – 8I D + 9 = 0 I D = mA I D = mA Replace in V GS equation V GS = 4 - I D V GS = V V GS = V Why choose V GS = V ? Because it is bigger than V TN
© Electronics 3. Get V DS equation and use the value of I D from step 2 Use KVL: I D R D + V DS + I D R S – 5 – 5 = (2) + V DS – 10 = 0 V DS = 10 – – = V 4. Calculate V DS sat 5. Confirm your assumption IDID IDID V DS sat = V GS – V TN = – 1 = V V DS > V DS sat CONFIRMED