1. Transistors Three-terminal devices with three doped silicon regions and two P-N junctions versus a diode with two doped regions and one P-N junction Two basic ways of implementation: Bipolar Junction Transistor (BJT) Field-Effect Transistor (FET)

2. Transistors Many types ! 3- terminal devices Made with semiconductor materials Used for … amplifier design and as switches ! (but many more … ) Common types: –BJT: Bipolar Junction Transistor –FET: Field Effect Transistor MOSFET: Metal Oxide Semiconductor FET MISFET: Metal Insulator Semiconductor FET CMOS Technology: Complementary Metal Oxide Semiconductor FETs !

3. Transistors Bipolar Junction Transistors n n p B C E C = collector B = base E = emitter NPN transistor

4. Transistors BJT

5. Transistors BJT

6. Transistors BJT PNP NPN

7. Typical Transistor Circuit Both DC and AC signals DC signals for “powering” up the transistor and establishing an “operating point” AC signals – what we want to “process” i.e. amplify

8. 8 Common Emitter Amplifier

9. 9 DC Equivalent Circuit

10. 10 Common Emitter Amplifier AC Equivalent Circuit

11. How Do We Handle Trans ?? Determine “operating mode” and replace transistor with appropriate model (linear!)

12. 12 Analysis Method

13. 13 Analysis Method

14. 14 a.Since V BB = 0.3V < 0.7V, transistor operates in CUTOFF region So I B = I C = 0. Write KVL equation around the input loop: V BB = 80k(I B ) + V BE V BE = 0.3 V Write KVL equation around the output loop: V CC = 2k(I C ) + V CE V CE = 10 V

15. 15 b.Since V BB = 2.7V > 0.7V, transistor is ON and V BE = 0.7V Write KVL equation around the input loop: V BB = 80k(I B ) + V BE I B = (2.7 – 0.7)/80k = 25  A Assuming ACTIVE mode, I C =  I B I C = 2.5 mA Write KVL equation around the output loop: V CE = V CC – 2k(I C ) = 5V > 0.2V, so transistor IS in active region

16. 16 c.Since V BB = 6.7V > 0.7V, transistor is ON and V BE = 0.7V Write KVL equation around the input loop: V BB = 80k(I B ) + V BE I B = (6.7 – 0.7)/80k = 75  A Assuming ACTIVE mode, I C =  I B I C = 7.5 mA Write KVL equation around the output loop: V CE = V CC – 2k(I C ) = –5V < 0.2V, so transistor is in SATURATION region I C = (V CC – V CE ) / 2k = 4.9 mA

17. Transistors Field-Effect Transistors

18. Transistors Field-Effect Transistors

19. Transistors FET

20. MOSFETs – Circuit Symbols n-MOS and p-MOS “working together” “n” and “p” for n- type and p-type semiconductor n-type: negative charges – electrons p-type: positive charges – “holes”

21. Transistors FET When V G is positive, electrons in the p-type substrate are attracted to the oxide–silicon interface, and form an n-type conduction channel. The electrical model is represented by resistors in series. The transistor is in its ON state. NMOS

22. Transistors FET When V G = 0, the area underneath the oxide layer is still p-type, which forms a “back-to-back” diode with the n region, as shown in the electrical representation. The transistor is in its OFF state. NMOS

23. Transistors FET PMOS

24. NMOS vs. PMOS - Operation

25. NMOS vs PMOS INPUTNMOS High “1”ON Low “0”OFF INPUTPMOS High “1”OFF Low “0”ON

26. NMOS Inverter What happens when V in is “high” ? i.e. logic level “1” What happens when V in is “low” ? i.e. logic level “0” 100011110100111010001110 INPUTOUTPUT High “1” Low “0”

27. CMOS Inverter

29. CMOS “Gate” ABOUT LO HI LO HI

30. CMOS “AND Gate” ABOUT LO HI LO HI

31. CMOS “AND Gate” ABOUT LO HI LO HI

32. CMOS “AND Gate” ABOUT LO HILO HILO HI

33. CMOS “AND Gate” ABOUT 000 010 100 111