1. Emitter-Stabilized Bias Circuit Load Line Analysis

2. The collector emitter loop equation defining load line is V CE =V CC -I C (R C +R E ) For I C =0mA V CE =V CC And for V CE =0, we get I c =V CC /(R C +R E ) Emitter-Stabilized Bias Circuit Load Line Analysis

3. Example Zammad is designing an amplifier circuit as shown in the figure. Find the highest voltage to which the base can be raised while the transistor remains in active mode. Assume α=1.

5. Lets consider that the voltage to which base can be raised for active operation be V. For the transistor to operate in active mode, consider V B =V C =V, therefore, for output loop, we have 10-4.7kI C -V C =0(1) Also for base-emitter loop we have V B -V BE -I E R E =0(2)  α=1, therefore I C =I E

6. From Equation (2) I E =(V B -V BE )/R E Putting the value of I E in equation (1) 10-(V B -V BE )R C /R E -V C =0 10-(V-0.7)4.7/3.3-V=0 3.3(10)-4.7V-3.29-V(3.3)=0  8V=29.71 V=3.71V

7. Example For the circuit shown find R E & R C.

8. Solution The given parameters are Ic=0.5mA & α=1, also V CB =2V Therefore, for the output loop we have by KVL (10-6)/0.5m=R C R C =2k 

9.  α=1, Therefore, I C =I E =0.5mA Hence for the base emitter loop by KVL (4-0.7)/0.5m=R E R E =2.6k 

10. DC BIASING-BJT Voltage Divider Bias Circuit

11. The input loop of the circuit will be Applying Thevenin’s theorem

12. DC BIASING-BJT Voltage Divider Bias Circuit R Th =R 1 IIR 2

13. E Th =V R2 =R 2 V cc /(R 1 +R 2 ) DC BIASING-BJT Voltage Divider Bias Circuit

14. The Thévenin Equivalent circuit is

15. Therefore the KVL equation will be E th -I B R B -V BE -I E R=0 Putting I E =(β+1)I B and solving for I B I B =(E Th— V BE )/(R Th +(β+1)R E ) Once I B is known the remaining problem may be solved exactly as in the previous configurations. DC BIASING-BJT Voltage Divider Bias Circuit

16. Example Find voltage at all nodes and current through all branches. Assume β=100.

17. Solution Using Thevenin’s theorem the circuit takes the form as shown in the figure. By writing V BB =15(R B2 )/(R B1 +R B2 ) =15(50)/150=5V & R BB =R B1 ||R B2 =100||50=33.3k 

18. Writing the KVL equation for the loop L V BB =I B R BB +V BE +I E R E Put I B =I E /(β+1)

19. The base current will be I B =1.29/101=0.0128mA Therefore the base voltage will be V B =V BE +I E R E =0.7+1.29(3)=4.57V Assuming active mode the collector current will be I C =αI E =0.99(1.29)=1.28mA AndV C =15-I C R C =15-1.28(5)=8.6V

20. Example: For the circuit shown find the voltages at all nodes and current through all branches.

21. Solution: Assume Q1 is in active mode, Therefore, from previous example V B1 =4.57V I E1 =1.29mA I B1 =0.0128mA I C1 =1.28mA (assuming I B1 negligibly small) Hence V C1 =15-I c1 R C1 =15-(1.28)5=8.6V

22. Now assume that emitter base junction of Q2 is forward bias, hence V E2 =V C1 +V EB =8.6+0.7=9.3V Also I E2 =(15-V E2 )/R E2 =(15-9.3)/2k =2.85mA

23. Now grounding of Q2 collector through R C2 shows, BC junction reverse bias I c2 =αI E2 =0.99(2.85m) =2.82mA (β=100)  V C2 =I c2 R c =7.62V

24. The value of V c2 is lower than V c1 =V B2 by 0.98V, therefore, Q2 is active. Now errors I B2 =I E2 /(β 2 +1) =2.85m/101=0.028 m A

25. Now doing iterations for I c1 and I B2 I Rc1 =I c1 -I B2 =1.25mA V c1= 15-5(1.252m)8.74V V E2 =8.74+0.7=9.44V I E2 =(15-9.44)/2k=2.78mA I c2 =0.99(2.78m)=2.75mA V c2 =2.75(2.7)=7.43V I B2 =2.78/101=0.0275mA

26. Biasing using two power supplies The loop equation for the loop marked as L is

27. Example The bias arrangement shown in the figure is to be used in common base amplifier. Design the circuit to establish a dc emitter current of 1mA and provide the highest possible gain while allowing for a maximum signal swing of ±2V at the collector. Use +10V and - 5V power supplies.

28. Solution Since the amplifier is to used in common base configuration, therefore the circuit will take the form as shown, hence R B =0

29. Considering the base- emitter junction forward biased, the emitter resistance can be found as R E =(-0.7-(-5))/1m=4.3k 

30. In order to allow for ±2V signal swing at the collector, while choosing as larger value of R C as possible, set V C =+2V, therefore - 2V signal would not saturate the BJT. Thus R C =(10-2)/I C =8/1mA=8k .