M2: Team Paradigm :: Milestone 4 2-D Discrete Cosine Transform Group M2: Tommy Taylor Brandon Hsiung Changshi Xiao Bongkwan Kim Project Manager: Yaping Zhan

M2: Team Paradigm Team Paradigm

M2: Team Paradigm Project status  Design Proposal (Complete)  Architecture Proposal (Complete) :Behavioral Verilog and test bench (Done)  Size estimates/floor plan (Complete) :Structural Verilog (Done) :Revised Floor plan (Done)  Full-chip schematic (Done)  Verilog verification of full-chip schematic (almost missing 2d, have 1d)  Critical Path Estimation

M2: Team Paradigm Transistor count and performance estimation : adderregisterROMControl logictotalpins 4x(15x24+14) = x16x15 =4320 8x16x2 = ~10.5k40 1DDCT module : 2DDCT = 2x1DDCT + SRAM ~ 29k throughputlatency 8 samples/64 cycle528 cycle Shift RegisterMuxesSRAM mux(44x20)+ ff(18x20)=

M2: Team Paradigm Transistor Numbers :mirror adder - 28 :mirror adder 16 bit :accumulator :and2 - 6 :bit address gen :compare3 - 4 :compare :control :decode :eightbitcounter :ff :flipflop - 12 :fourbitcompare :fourbitcounter :p to s :reg20bit :shiftreg :shiftreg20bit :sram sense amp - 5 :statereg - 24 :threebitcounter - 78 :tranmission - 2 :twobitcounter - 52 :twobitmux :xor2 - 8 :halfadder - 14 :midbuf

M2: Team Paradigm Larger Components :Control Logic (616)

M2: Team Paradigm Larger Components :In buffer (4226)

M2: Team Paradigm Larger Components Breakdown :Mirror Adder: (28) :16 bit – (448), 20 bit (560)

M2: Team Paradigm Larger Components :Mid Buffer (960)

M2: Team Paradigm Larger Components :Bitaddress_Generator (960)

M2: Team Paradigm Larger Components :Shift Register 16bit (832), 20bit (1200)

M2: Team Paradigm Larger Components :Accumulator (1076)

M2: Team Paradigm Larger Components :1D Dct (14026)

M2: Team Paradigm Larger Components :Parallel to Serial (884)

M2: Team Paradigm Larger Components :2d DCT (28200)

M2: Team Paradigm Old layout proposal Sub Add Control logic rom shift reg 16bit 1x8 demux 16bit 4x1 mux 16bit 4x1 mux reg 16bit 1x4 demux 4bit 16x1 mux Add rom Add 4bit 16x1 mux 16bit 1x4 demux 16bit 2x1 mux reg eg 600u 150u

M2: Team Paradigm Overall floorplan 1D DCT 16 x 64 SRAM x 600 = 300,000um 2

M2: Team Paradigm New Layout Proposal rom shift reg reg 4bit 16x1 mux Add rom shift reg Add 4bit 16x1 mux 16bit 4x1 mux reg Add reg Add 16bit 4x1 mux ctrl 500u 200u

M2: Team Paradigm Overall floorplan 1D DCT 16 x 64 SRAM x 600 = 300,000um 2

M2: Team Paradigm ::conclusion & questions :29k too much? : How to simulate individual parts.