Viterbi Decoder: Presentation #7 M1 Overall Project Objective: Design a high speed Viterbi Decoder Stage 7: 1st Mar Component layout (corrected) Design Manager: Yaping Zhan Omar Ahmad Prateek Goenka Saim Qidwai Lingyan Sun

Status , Integrated Circuits Design Project Design Proposal (Done) Architecture Proposal (Done) Gate level Design(Done) Component Layout (DRC & LVS): (Done) Major Blocks Layout: (Almost) BCU: 100% Trace Back: 100% ACS/ML Search: 80% To be done: Chip Layout Spice Simulation of Entire Chip

18-525, Integrated Circuits Design Project Old Floorplan , Integrated Circuits Design Project M4 M2 M3

New Floorplan , Integrated Circuits Design Project

Dimensions , Integrated Circuits Design Project Old: 318 x 285 sq. um ~22,500 transistors Density – New: 319 x 219 sq. um ~21,000 transistors Density –

3 bits stage in MLSearch(Old) , Integrated Circuits Design Project

3 bits stage in MLSearch(New)

Old ACS Unit (Schematic) , Integrated Circuits Design Project

New ACS Unit (Schematic) , Integrated Circuits Design Project

Top Level Schematic (Old) , Integrated Circuits Design Project

Top Level Schematic (New)

Simulations still match!! , Integrated Circuits Design Project

Trace Back , Integrated Circuits Design Project

BCU Cell

BCU Unit (Layout) , Integrated Circuits Design Project

New Comparator Layout

18-525, Integrated Circuits Design Project Comparator 8b (50 fF) Propagation Delay Worst Case: 2.23 ns

New comparator Propagation Delay Worst Case = 812 ps.

New comparator falling Worst Case = 805 ps.

18-525, Integrated Circuits Design Project Questions?