M2: Team Paradigm :: Milestone 3 2-D Discrete Cosine Transform Group M2: Tommy Taylor Brandon Hsiung Changshi Xiao Bongkwan Kim Project Manager: Yaping Zhan

M2: Team Paradigm Team Paradigm

M2: Team Paradigm Project status  Revisal of Floorplan -->Results Today

M2: Team Paradigm Transistor count and performance estimation : adderregisterROMControl logictotalpins 4x(15x24+14) = x16x15 =4320 8x16x2 = ~10.5k40 1DDCT module : 2DDCT = 2x1DDCT + SRAM ~ 29k throughputlatency 8 samples/64 cycle528 cycle Shift RegisterMuxesSRAM mux(44x20)+ ff(18x20)=

M2: Team Paradigm Layout Size Proposal :Using a reference of layout of basic gates -And referencing devices from 322 to get accurate sizing :Furthermore we did this on basic gates, then scale accordingly for larger instances -for example: a 20 16bit registers will just be the stacked on top of each other -->single register mainly length multiplied by 16 then by 20 :Our design has total of approx 29k -add space for wiring... cannot give an accurate measurement for :Total area estimation of square area = 300,000um 2

M2: Team Paradigm Basic Component Breakdown single bit items Mirror Adder: gate adder: Register: half adder: nand: nor: xor: inv: length width Mux 2: Shift Register: Mux 4: length width

M2: Team Paradigm Larger Components Breakdown :Mirror Adder: 28 Transistors including inverters -Faster than 5 gate adder -for 16bit multiply single cell by 16 -approx (12x16) x 7 = 198 x 7 -Subtractor only slightly larger -due to inverters Adder/Sub

M2: Team Paradigm Larger Components :Mux -2:1mux x :1mux – 8.91 x bit = 9x(16 x 19) :Control Logic -Mixture of basic gates -estimate 1000 trans 16bit 4x1 mux

M2: Team Paradigm Larger Components :Shift Register -16 x 18.6 single bit cell -20 bit = (18.6 x 20) x 16 :Basic Register x 5.02 single bit cell -16 bit registers x 5 shift reg reg

M2: Team Paradigm Larger Components :nand ROM (due to size) -there are two -1 rom = banks -1 bank = 16 words -1 word = 16 bits :each bank: 10u x 12u -total size = 120u --> 1 rom = >12 x 48

M2: Team Paradigm Old Layout Proposal 1D DCT MUX 4x1 32' Sub Add DeMux 4x1 DeMux 4x1 Reg 8x16' R7 R0 R6 R1 R5 R2 R4 R1 Take bits Take bits Add Rom Shift Reg Control Logic approx. 220,000u 220u x 100u

M2: Team Paradigm New layout proposal Sub Add Control logic rom shift reg 16bit 1x8 demux 16bit 4x1 mux 16bit 4x1 mux reg 16bit 1x4 demux 4bit 16x1 mux Add rom Add 4bit 16x1 mux 16bit 1x4 demux 16bit 2x1 mux reg eg 600u 150u

M2: Team Paradigm Overall floorplan 1D DCT 16 x 64 SRAM x 600 = 300,000um 2

M2: Team Paradigm ::conclusion & questions :Implementing 2D DCT :Roughly 29k transistor count :Will try to optimize design further and enhance performance