ENEE 408C Lab Capstone Project: Digital System Design Spring 2005 Class Web Site: e408c

TA’s Information Alessandro Geist Office Hours: TBD

What we do in lab Review of lecture In-class quizzes Question & Answer Work on projects

What you expect to learn Digital system(hardware) design process –Design description ? Yes –Synthesis ? Yes –Implementation ? Yes, but to some extent –Fabrication ? No! Use of design tools –Verilog HDL language –Xilinx FPGA tool package Spirit of team work

Platform & Software to use SUN OS 5.8 or X-Win32 Xilinx Modelsim Xilinx ISE Project Navigator

Modules and Primitives Modules module FA ( ); …endmodulePrimitives nand g( ) Has to specify inputs and outputs Can have multiple outputs module instantiation FA My_FA(<port_list); First port is output Have only one output Primitives instantiation nand G( );

Registers and Nets reg –has default size of 1 bit –stores information while the program executes –acts like variables in procedure languages wire –establish connectivity between design objects –acts like wires in physical circuit –value changes as long as the value in the entity that drives it changes integer –a reg with fixed size at least 32 bits

Port Declaration input –Always wires inout output –Register or wire All are implicitly wires.

Example: Half Adder module halfAdder (SUM, CARRY, A, B); input A, B; input A, B; output SUM, CARRY; output SUM, CARRY; assign SUM = A ^ B; // exclusive OR assign SUM = A ^ B; // exclusive OR assign CARRY = A & B; // AND assign CARRY = A & B; // ANDendmodule

Half Adder // halfadder.v /* In the module interface definition, each port must correspond to an input, output, or inout definition. */ an input, output, or inout definition. */ module halfAdder (A, B, SUM, CARRY); module halfAdder (A, B, SUM, CARRY); input A, B; input A, B; output SUM, CARRY; output SUM, CARRY; /* -- The #N syntax indicates a "delay": /* -- The #N syntax indicates a "delay": suspend an operation until N time units of delay elapse. suspend an operation until N time units of delay elapse. -- SUM and CARRY are implicitly defined as nets (wires). */ -- SUM and CARRY are implicitly defined as nets (wires). */ assign #2 SUM = A ^ B; // exclusive OR operation assign #2 SUM = A ^ B; // exclusive OR operation assign #5 CARRY = A & B; // bitwise AND operation assign #5 CARRY = A & B; // bitwise AND operation endmodule endmodule