1. Slide 1 3.VHDL/Verilog Description Elements

2. Slide 2 To create a digital component, we start with…? The component’s interface signals Defined in MODULE Module contains the WHOLE code of the component, including the definitions for Ports – input, output and inout signals Parameters – can be overwritten from the upper hierarchical level Verilog Description Elements

3. Slide 3 General Form Definition Naming Conventions - MUST be there [name] - Optional (does not have to be present) - Either name1 or name 2 [name1 | name2] – Optional name1 or name2 Example: port definition: [type] [size] ; OR: [wire | reg] [size] ;

4. Slide 4 Symbol Drawing Elements My_module A[7:0] B[7:0] CLK DATA[7:0] CE 8 8 8 Input and Output Ports: Arrowheads will be usually missing Usually, inputs are at the left side, outputs at the right side. If not, arrows indicating direction should be present Inout ports: arrowheads should be present Arrowhead indicating that is a clock signal (convention!) These are only helpers, indicating the signal width. Recommended to be present

5. Slide 5 Symbol Drawing Elements My_module A[7:0] B[7:0] CLK DATA[7:0] CE 8 8 8 Bus label designators are not part of the signal name!!! Do not write input A[7:0]! Syntactically is correct, but it will create an array of 8 signals, each signal of one bit wide Do not use arrays for input/output ports! The signal name is A The bus designator is [7:0] Correct form: input [7:0] A

6. Slide 6 Verilog Module Definition General Form Prior Verilog 2001: module [#(paramater_list)] ( ); //for each port in the list: [size] name; Example: My_module module My_module (A, B, CLK, DATA, CE); input [7:0] A; input [7:0] B; input CLK; inout [7:0] DATA; output CE; … endmodule My_module A[7:0] B[7:0] CLK DATA[7:0] CE 8 8 8 This is a LIST of ports, end each element with, except the last one This is NOT a list of ports but port declaration statements, end each statement with ;

7. Slide 7 Verilog Module Definition General Form Newer form – more compact module [#(parameter_list)] ( ); Example: My_module module My_module (input [7:0] A, input [7:0] B, input CLK, inout [7:0] DATA, output CE); … endmodule My_module A[7:0] B[7:0] CLK DATA[7:0] CE 8 8 8 This is a LIST of ports, end each element with, except the last one

8. Slide 8 Port directions input – Signal values can be ONLY READ, not written output – Signal values can be both read and written (assigned), with the restriction: A SIGNAL CAN BE ASSIGNED IN ONLY ONE PLACE, i.e. One assign statement (if the signal is wire type), or One always statement (if the signal is reg type) inout - Bidirectional signal (tri-state) - Although newer FPGA devices can have tristate buffers on-chip, it is recommended to be used only for connections outside the chip - Recommendations: - Use two different signals for reading and assigning input values - Use a separate control signal to control the direction of the inout signal

9. Slide 9 VHDL ENTITY Definition General Form entity is generic ( : := ;... ); port ( : ; …); end [entity] ; Example: My_module entity My_module is port (A: in std_logic_vector (7 downto 0); B: in std_logic_vector (7 downto 0); CLK: in std_logic; DATA: inout std_logic_vector (7 downto 0); CE: out std_logic ); end My_module; My_module A[7:0] B[7:0] CLK DATA[7:0] CE 8 8 8 This is a LIST of port statements, end each element with ; except the last one VHDL: out ports can be written in only one place, but CAN NOT BE READ! An internal signal has to be declared and used to read the output port

10. Slide 10 Signal and port modes wire – Can be assigned only in a concurrent statement (assign) – Cannot have initial value! Example: wire s = 0; … assign s = … //NOT ALLOWED! s is already constant (0) Otherwise, the synthesizer would be forced to create a circuit like: reg – Can be assigned only in a sequential statement (always) – Can have initial value Example: reg q = 0; //Allowed

11. Slide 11 Port directions linked to modes input – By default, considered as wire, cannot be assigned anyway output, inout – If their type is not specified, by default are considered as wire – If needed to assign output ports in always statements, specify reg in port declaration – Example: output reg [7:0] Dout, output reg CE,... From upper level hierarchy, output or inout ports are always seen by default as wire Recommended design practice: declare output ports as wire Use an internal signal with _reg suffix and assign the output port to it In this way, port declarations does not have to change, only internal code