1. ELEN 468 Lecture 21 ELEN 468 Advanced Logic Design Lecture 2 Hardware Modeling

2. ELEN 468 Lecture 22 Overview Verilog modules Verilog primitives Structural descriptions Behavioral descriptions Hierarchical design Language conventions

3. ELEN 468 Lecture 23 Verilog Module Description of internal structure/function Implicit semantic of time associated with each data object/signal Implementation is hidden to outside world Communicate with outside through ports Port list is optional Achieve hardware encapsulation module Add_half ( sum, c_out, a, b ); inputa, b; outputsum, c_out; wire c_out_bar; xor (sum, a, b); nand (c_out_bar, a, b); not (c_out, c_out_bar); endmodule c_out a b sum c_out_bar

4. ELEN 468 Lecture 24 Behavioral Description module Add_half ( sum, c_out, a, b ); inputa, b; outputsum, c_out; assign { c_out, sum } = a + b; // Continuous assignment endmodule a b Add_half sum c_out Concatenation

5. ELEN 468 Lecture 25 Module Instantiation Accomplished by entering Module name as a module item within a parent module Signal identifiers at appropriate ports Module instantiation needs a module identifier A module is never declared within another module The order of ports in instantiation usually matches the order in module declaration

6. ELEN 468 Lecture 26 Design a Full Adder sum HA = a  b c_out HA = a b sum FA = a  b  c_in c_out FA = a b + b c_in + a c_in sum FA = (a  b)  c_in c_out FA = (a  b) c_in + a b a + b = a(b+b’) + (a+a’)b = ab + ab’ + a’b ab + bc + ac = ab + (a+b)c = ab + (a  b+ab)c = ab + a  b c+abc = ab + (a  b)c

7. ELEN 468 Lecture 27 Full Adder  2 Half Adders sum HA = a  b c_out HA = a b sum FA = (a  b)  c_in c_out FA = (a  b) c_in + a b Add_half (a  b)c_in a b Add_half abab ab c_in (a  b)  c_in (a  b) c_in + a b

8. ELEN 468 Lecture 28 Module instance name Full Adder in Verilog module Add_full ( sum, c_out, a, b, c_in );// parent module input a, b, c_in; output c_out, sum; wire w1, w2, w3; Add_half M1 ( w1, w2, a, b ); Add_half M2 ( sum, w3, w1, c_in );// child module or ( c_out, w2, w3 );// primitive instantiation endmodule module Add_full ( sum, c_out, a, b, c_in );// parent module input a, b, c_in; output c_out, sum; wire w1, w2, w3; Add_half M1 ( w1, w2, a, b ); Add_half M2 ( sum, w3, w1, c_in );// child module or ( c_out, w2, w3 );// primitive instantiation endmodule Add_half (a  b)c_in a b Add_half abab ab c_in (a  b)  c_in (a  b) c_in + a b w1 w2 w3 sum c_out

9. ELEN 468 Lecture 29 Verilog Primitives Basic element to build a module, such as nand, nor, buf and not gates Never used stand-alone in design, must be within a module Pre-defined or user-defined Identifier (instance name) is optional Output is at left-most in port list Default delay = 0

10. ELEN 468 Lecture 210 Symmetric Delay Assignment module AOI_4 ( y, x1, x2, x3, x4 ); input x1, x2, x3, x4; output y; wire y1, y2; and#1 ( y1, x1, x2 ); and #1 ( y2, x3, x4 ); nor#1 ( y, y1, y2 ); endmodule x1 x2 x3 x4 y1 y2 y

11. ELEN 468 Lecture 211 Asymmetric Delay Assignment module nand1 ( O, A, B ); input A, B; output O; nand ( O, A, B ); specify specparam T01 = 1.13:3.09:7.75; T10 = 0.93:2.50:7.34; ( A=>O ) = ( T01, T10 ); ( B=>O ) = ( T01, T10 ); endspecify endmodule Min delay Typical delay Max delay Falling time Rising time

12. ELEN 468 Lecture 212 Smart Primitives module nand3 ( O, A1, A2, A3 ); input A1, A2, A3; outputO; nand ( O, A1, A2, A3 ); endmodule Same primitive can be used to describe for any number of inputs This works for only pre-defined primitives, not UDP

13. ELEN 468 Lecture 213 Explicit Structural Descriptions module AOI_4 ( y, x1, x2, x3, x4 ); input x1, x2, x3, x4; output y; wire y1, y2; and#1 ( y1, x1, x2 ); and #1 ( y2, x3, x4 ); nor#1 ( y, y1, y2 ); endmodule x1 x2 x3 x4 y1 y2 y

14. ELEN 468 Lecture 214 Implicit Structural Description module nand2_RTL ( y, x1, x2 ); input x1, x2; outputy; assign y = x1 ~& x2; endmodule module nand2_RTL ( y, x1, x2 ); input x1, x2; outputy; wire y = x1 ~& x2; endmodule Explicit continuous assignmentImplicit continuous assignment Continuous assignment – Static binding between LHS and RHS No mechanism to eliminate or alter the binding

15. ELEN 468 Lecture 215 Multiple Instantiations module multiple_gates ( y1, y2, y3, a1, a2, a3, a4 ); input a1, a2, a3, a4; outputy1, y2, y3; nand #1 G1(y1, a1, a2, a3), (y2, a2, a3, a4), (y3, a1, a4); endmodule module multiple_gates ( y1, y2, y3, a1, a2, a3, a4 ); input a1, a2, a3, a4; outputy1, y2, y3; nand #1 G1(y1, a1, a2, a3), (y2, a2, a3, a4), (y3, a1, a4); endmodule The delay element #1 is effective for all instances

16. ELEN 468 Lecture 216 Multiple Assignments module multiple_gates ( y1, y2, y3, a1, a2, a3, a4 ); input a1, a2, a3, a4; outputy1, y2, y3; assign #1 y1 = a1 ^ a2, y2 = a2 | a3, y3 = a1 + a4; endmodule module multiple_gates ( y1, y2, y3, a1, a2, a3, a4 ); input a1, a2, a3, a4; outputy1, y2, y3; assign #1 y1 = a1 ^ a2, y2 = a2 | a3, y3 = a1 + a4; endmodule

17. ELEN 468 Lecture 217 Structural Connections By order By name Empty port module child( a, b, c ); … endmodule module parent; wire u, v, w; child m1( u, v, w ); child m2(.c(w),.a(u),.b(v) ); child m3( u,, w ); endmodule

18. ELEN 468 Lecture 218 Behavioral Descriptions: Data Flow module and4( y, x ); input [3:0]x; outputy; assign y = & x; endmodule module Flip_flop ( q, data_in, clk, rst ); input data_in, clk, rst; output q; reg q; always @ ( posedge clk ) begin if ( rst == 1) q = 0; else q = data_in; end endmodule

19. ELEN 468 Lecture 219 Behavioral Descriptions: Algorithm-based module and4_algo ( y, x ); input [3:0]x; output y; reg y; integerk; always @ ( x ) begin: and_loop y = 1; for ( k = 0; k <= 3; k = k+1 ) if ( x[k] == 0 ) begin y = 0; disable and_loop; end endmodule module and4_algo ( y, x ); input [3:0]x; output y; reg y; integerk; always @ ( x ) begin: and_loop y = 1; for ( k = 0; k <= 3; k = k+1 ) if ( x[k] == 0 ) begin y = 0; disable and_loop; end endmodule Optional name Enable “disable” x[0] or x[1] or x[2] or x[3]

20. ELEN 468 Lecture 220 Description Styles Explicit structural Implicit structural Explicit continuous assignment Implicit continuous assignment Data flow/RTL Algorithm-based Structural Behavioral

21. ELEN 468 Lecture 221 Hierarchical Description Add_half a b c_in M1 M2 sum c_out xornandnot Add_half xornandnot Add_halfor Add_full M1 M2 Nested module instantiation to arbitrary depth

22. ELEN 468 Lecture 222 Structured Design Methodology Design: top-down Verification: bottom-up Example 2.18 in textbook pg 45

23. ELEN 468 Lecture 223 Arrays of Instances module flop_array(q, in, clk, rst); input [7:0]in; inputclk, rst; output [7:0] q; Flip_flop M[7:0] (q, in, clk, rst); endmodule module pipeline(q, in, clk, rst ); input [7:0]in; inputclk, rst; output [7:0] q; wire [23:0]pipe; flop_array M[3:0] ({q, pipe}, {pipe, in}, clk, rst); endmodule rst clk in[7:0]q[7:0]pipe[7:0]pipe[23:16]

24. ELEN 468 Lecture 224 Verilog for Synthesis module comp(lt,gt,eq,a0,a1,b0,b1); inputa0, a1, b0, b1; outputlt, gt, eq; wirew1, w2, w3, w4, w5, w6, w7; or (lt, w1, w2, w3); nor (gt, lt, eq); and (w1, w6, b1); and (w2, w6, w7, b0); and (w3, w7, b0, b1); not (w6, a1); not (w7, a0); xnor (w4, a1, b1); xnor (w5, a0, b0); endmodule module comp(lt,gt,eq,a0,a1,b0,b1); inputa0, a1, b0, b1; outputlt, gt, eq; wirew1, w2, w3, w4, w5, w6, w7; or (lt, w1, w2, w3); nor (gt, lt, eq); and (w1, w6, b1); and (w2, w6, w7, b0); and (w3, w7, b0, b1); not (w6, a1); not (w7, a0); xnor (w4, a1, b1); xnor (w5, a0, b0); endmodule module comp(lt, gt, eq, a, b); input [1:0]a, b; outputlt, gt, eq; assign it = ( a < b ); assign gt = ( a > b ); assign eq = ( a == b ); endmodule module comp(lt, gt, eq, a, b); input [1:0]a, b; outputlt, gt, eq; assign it = ( a < b ); assign gt = ( a > b ); assign eq = ( a == b ); endmodule Figure 2.30 Figure 2.28

25. ELEN 468 Lecture 225 Language Conventions Case sensitive Instance of a module must be named Keywords are lower-case Comments start with “//”, or blocked by “/* */”

26. ELEN 468 Lecture 226 Numbers in Verilog Binary, decimal, octal, hex … Table 2.2