1. ELEN 468 Lecture 151 ELEN 468 Advanced Logic Design Lecture 15 Synthesis of Language Construct I

2. ELEN 468 Lecture 152 Synthesis of Nets module and3( y, a, b, c ); input a, b, c; output y; wire y1; assign y1 = a & b; assign y = y1 & c; endmodule module and3( y, a, b, c ); input a, b, c; output y; wire y1; assign y1 = a & b; assign y = y1 & c; endmodule An explicitly declared net may be eliminated in synthesis Primary input and output (ports) are always retained in synthesis Synthesis tool will implement trireg, tri0 and tri1 nets as physical wires a b c y

3. ELEN 468 Lecture 153 Synthesis of Register Variables A hardware register will be generated for a register variable when It is referenced before value is assigned in a behavior Assigned value in an edge-sensitive behavior and is referenced by an assignment outside the behavior Assigned value in one clock cycle and referenced in another clock cycle Multi-phased latches may not be supported in synthesis

4. ELEN 468 Lecture 154 Synthesis of Integers Initially implemented as a 32-bit register Always specify size when declare a constant For example, parameter a = 3’b7 will consume 3 bits while default is 32 bits

5. ELEN 468 Lecture 155 Unsupported Data Types real time realtime string

6. ELEN 468 Lecture 156 Synthesis of Memories No direct support Usually implemented as array of registers Not efficient as external memory Minimize the usage of such memory

7. ELEN 468 Lecture 157 Synthesis of “x” and “z” A description that uses explicit “x” or “z” values for data selection cannot be synthesized The only allowed usage of “x” is in casex and casez statements The only allowed use for “z” is in constructs that imply 3-states device If a UDP assigns a value of “x” to a wire or reg, it will be treated as “don’t care”

8. ELEN 468 Lecture 158 Synthesis of Arithmetic Operators If corresponding library cell exists, an operator will be directly mapped to it Synthesis tool may select among different options in library cell, for example, when synthesize an adder Small wordlength -> ripple-carry adder Long wordlength -> carry-look-ahead adder Need small area -> bit-serial adder Implementation of “*” and “/” May be inefficient when both operands are variables If a multiplier or the divisor is a power of two, can be implemented through shift register

9. ELEN 468 Lecture 159 Synthesis of Shift Operators Synthesis tools normally support shifting by a constant number of bits Cannot support a variable shift

10. ELEN 468 Lecture 1510 Relational Operators Relational operators (, >=, <= ) can be implemented through Combinational logic Adder/subtractor  In bit-extended format  Calculate A – B, check extended bit of result 0 -> A >= B 1 -> A < B module compare ( lt, gt, eq, A, B ); input A, B; output lt, gt, eq; assign lt = ( A < B ); assign gt = ( A > B ); assign eq = ( A == B ); endmodule module compare ( lt, gt, eq, A, B ); input A, B; output lt, gt, eq; assign lt = ( A < B ); assign gt = ( A > B ); assign eq = ( A == B ); endmodule

11. ELEN 468 Lecture 1511 Synthesis of Identity Operators The logical identity operators ( ==, != ) and the case identity operators ( ===, !== ) are normally synthesized to combinational logic

12. ELEN 468 Lecture 1512 Reduction, Bitwise and Logical Operators They are translated into a set of equivalent Boolean equations and synthesized into combinational logic

13. ELEN 468 Lecture 1513 Conditional Operator The conditional operator ( ? … : ) synthesizes into library muxes or gates that implement the functionality of a mux The expression to the left of ? is formed as control logic for the mux

14. ELEN 468 Lecture 1514 Concatenation Operator Equivalent to a logical bus No functionality of its own Generally supported by synthesis tool

15. ELEN 468 Lecture 1515 Grouping of Operators module operator_group ( sum1, sum2, a, b, c, d ); input a, b, c, d; output sum1, sum2; assign sum1 = a + b + c + d; assign sum2 = ( a + b ) + ( c + d ); endmodule module operator_group ( sum1, sum2, a, b, c, d ); input a, b, c, d; output sum1, sum2; assign sum1 = a + b + c + d; assign sum2 = ( a + b ) + ( c + d ); endmodule adder sum2 adder sum1 a b c d

16. ELEN 468 Lecture 1516 Synthesis of Assignment Support by synthesis is vendor-specific Continuous assignment can be mapped directly to combinational logic Procedural assignment, LHS must be register variable Procedural continuous assignment Supported by some tools PCA to register cannot be overwritten by any procedural assignment

17. ELEN 468 Lecture 1517 Expression Substitution in Procedural Assignment module multiple_assign ( out1, out2, a, b, c, d, sel, clk ); output [4:0] out1, out2; input [3:0] a, b, c, d; input sel, clk; reg [4:0] out1, out2; always @ ( posedge clk ) begin out1 = a + b; out2 = out1 + c; if ( sel == 1’b0 ) out1 = out2 + d; end endmodule module multiple_assign ( out1, out2, a, b, c, d, sel, clk ); output [4:0] out1, out2; input [3:0] a, b, c, d; input sel, clk; reg [4:0] out1, out2; always @ ( posedge clk ) begin out1 = a + b; out2 = out1 + c; if ( sel == 1’b0 ) out1 = out2 + d; end endmodule module multiple_assign ( out1, out2, a, b, c, d, sel, clk ); output [4:0] out1, out2; input [3:0] a, b, c, d; input sel, clk; reg [4:0] out1, out2; always @ ( posedge clk ) begin out2 = a + b + c; if ( sel == 1’b0 ) out1 = a + b + c + d; else out1 = a + b; end endmodule module multiple_assign ( out1, out2, a, b, c, d, sel, clk ); output [4:0] out1, out2; input [3:0] a, b, c, d; input sel, clk; reg [4:0] out1, out2; always @ ( posedge clk ) begin out2 = a + b + c; if ( sel == 1’b0 ) out1 = a + b + c + d; else out1 = a + b; end endmodule

18. ELEN 468 Lecture 1518 Exercise 5

19. ELEN 468 Lecture 1519 Problem 2.3 Write structural description with primitive gates for the Boolean equation: y1 = a0’●b2 + a2’ ● a0 ● b2 + a0 ● b1’ ● b0 module P23(y1, a0, a2, b0, b1, b2); input a0, a2, b0, b1, b2; output y1; wire not_a0, not_a2, not_b1, t1, t2, t3; not(not_a0, a0); and(t1, not_a0, b2); not(not_a2, a2); and(t2, not_a2, a0, b2); not(not_b1, b1); and(t3, a0, not_b1, b0); or(y1, t1, t2, t3); endmodule

20. ELEN 468 Lecture 1520 Problem 2.4 Write Verilog code using continuous assignment for the Boolean equation: y1 = a0’●b2 + a2’ ●a0●b2 + a0● b1’ ●b0 module P23(y1, a0, a2, b0, b1, b2); input a0, a2, b0, b1, b2; output y1; assign y1= (~a0)&b2 | (~a2)&a0&b2 | (~b1)&b0; endmodule

21. ELEN 468 Lecture 1521 Problem 2.11 Using Verilog predefined primitive, write a description of the circuit below: module p211(q, qb, set, rst); input [7:0] set, rst; output [7:0] q, qb; nor [7:0] (q, rst, qb); nor [7:0] (qb, set, q); endmodule

22. ELEN 468 Lecture 1522 Problem 2.12 Using continuous assignment, write a description of the circuit below: module p212(q, qb, set, rst); input [7:0] set, rst; output [7:0] q, qb; assign q=~(rst | qb); assign qb = ~(set | q); endmodule

23. ELEN 468 Lecture 1523 Problem 2.21 Which of the following assignments have correct syntax? What is stored in the memory? a.A=8’b1010000 0101 b.B=5’o9wrong c.C=12’HAA0000 1010 1010 d.D=4’BBBwrong e.E=4d’x3wrong f.F=4’hzzzzz g.G=4’O8wrong h.H=8’hz9zzzz1001