Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 13 1 ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Pseudo-nMOS, Dynamic CMOS and Domino CMOS Logic Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 132 Why Not Static CMOS? Advantages: Static (robust) operation, low power, scalable with technology. Advantages: Static (robust) operation, low power, scalable with technology. Disadvantages: Disadvantages: Large size: An N input gate requires 2N transistors. Large size: An N input gate requires 2N transistors. Large capacitance: Each fanout must drive two devices. Large capacitance: Each fanout must drive two devices. Alternatives: Pass-transistor logic (PTL), pseudo-nMOS, dynamic CMOS, domino CMOS. Alternatives: Pass-transistor logic (PTL), pseudo-nMOS, dynamic CMOS, domino CMOS.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 133 A Pseudo-nMOS Gate PUN PDN VDD CMOS Gate PDN VDD Pseudo-nMOS Gate Output Inputs Output

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 134 Pseudo-nMOS NOR VDD Input 1 Output Input 2 Input 3

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 135 Pseudo-nMOS NAND VDD Input 1 Output Input 2

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 136 Pseudo-nMOS Inverter VDD Input Output

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 137 Inverter Characteristics W/L p = 4 W/L p = 2 W/L p = 0.25 W/L p = 0.5 W/L p = Input voltage, V Output voltage, V Nominal device: W 0.5μ ── =──── = 2 L n 0.25μ

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 138 Performance of Inverter Size, W/L p Logic 0 voltage Logic 0 static power Delay 0 → V 564 μW 14 ps V 298 μW 56 ps V 160 μW 123 ps V 80 μW 268 ps V 41 μW 569 ps J. M. Rabaey, A. Chandrakasan and B. Nokolić, Digital Integrated Circuits, Upper Saddle River, New Jersey: Pearson Education, 2003, page 262.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 139 Negative Aspects of Pseudo-nMOS Output 0 state is ratioed logic. Output 0 state is ratioed logic. Faster gates mean higher static power. Faster gates mean higher static power. Low static power means slow gates. Low static power means slow gates.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1310 A Dynamic CMOS Gate PDN VDD Inputs Output CK CLCL Precharge transistor Evaluate transistor

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1311 Two-Phase Operation in a Vector Period PhaseCKInputsOutput Prechargelow don’t care high Evaluationhigh Valid inputs Valid outputs

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture Input NAND Dynamic CMOS Gate Output = CK’ + (ABCD)’∙ CK CLCL CK A B C D CK VDD t L→H ≈ 0

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1313 Characteristics of Dynamic CMOS Nonratioed logic – sizing of pMOS transistor is not important for output levels. Nonratioed logic – sizing of pMOS transistor is not important for output levels. Smaller number of transistors, N+2 vs. 2N. Smaller number of transistors, N+2 vs. 2N. Larger precharge transistor reduces output fall time, but increases precharge power. Faster switching due to smaller capacitance. Larger precharge transistor reduces output fall time, but increases precharge power. Faster switching due to smaller capacitance. Static power – negligible. Static power – negligible. Short-circuit power – none. Short-circuit power – none. Dynamic power Dynamic power no glitches – following precharge, signals can either make transitions only in one direction, 1→0, or no transition, 1→1. no glitches – following precharge, signals can either make transitions only in one direction, 1→0, or no transition, 1→1. only logic transitions – all nodes at logic 0 are charged to VDD during precharge phase. only logic transitions – all nodes at logic 0 are charged to VDD during precharge phase.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1314 Switching Speed and Power Fewer transistors mean smaller node capacitance. Fewer transistors mean smaller node capacitance. No short-circuit current to slow down discharging of capacitance. No short-circuit current to slow down discharging of capacitance. Only dynamic power consumed, but can be higher than CMOS. Only dynamic power consumed, but can be higher than CMOS.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1315 Logic Activity Probability of 0 → 1 transition: Probability of 0 → 1 transition: Static CMOS, p0 p1 = p0(1 – p0) Static CMOS, p0 p1 = p0(1 – p0) Dynamic CMOS, p0 ≥ p0 p1 Dynamic CMOS, p0 ≥ p0 p1 Example: 2-input NOR gate Example: 2-input NOR gate Static CMOS, Pdyn = C L V DD 2 f CK Static CMOS, Pdyn = C L V DD 2 f CK Dynamic CMOS, Pdyn = 0.75 C L V DD 2 f CK Dynamic CMOS, Pdyn = 0.75 C L V DD 2 f CK p1=0.5 p1=0.25 p0=0.75

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1316 Charge Leakage Output A’ CLCL CK A=0 CK VDD CK A’ Time Precharge Evaluate Ideal Actual J. M. Rabaey, A. Chandrakasan and B. Nokolić, Digital Integrated Circuits, Upper Saddle River, New Jersey: Pearson Education, 2003.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1317 Bleeder Transistor Output CLCL CK A B C D CK VDD Output CLCL CK A B C D CK VDD

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1318 A Problems With Dynamic CMOS CK A=0→1 CK VDD CK A B C B J. M. Rabaey, A. Chandrakasan and B. Nokolić, Digital Integrated Circuits, Upper Saddle River, New Jersey: Pearson Education, CK VDD C prech. evaluate

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1319 Remedy Set all inputs to gates to 0 during precharge. Set all inputs to gates to 0 during precharge. Since precharge raises all outputs to 1, inserting inverters between gates will do the trick. Since precharge raises all outputs to 1, inserting inverters between gates will do the trick.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1320 Domino CMOS CK A=0→1 CK VDD CK A B C B R. H. Krambeck, C. M. Lee and H.-F. S. Law, “High-Speed Compact Circuits with CMOS,” IEEE J. Solid-State Circuits, vol. SC-17, no. 3, pp , June CK VDD C prech. evaluate

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1321 Bleeder in Domino CMOS Output CLCL CK A B C D CK VDD

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1322 Logic Mapping for Noninverting Gates ABCDEFGHABCDEFGH ABC G+H AND OR AND/OR XYXY Y ABC D E F G+H

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1323 Selecting a Logic Style Static CMOS: most reliable and predictable, reasonable in power and speed, voltage scaling and device sizing are well understood. Static CMOS: most reliable and predictable, reasonable in power and speed, voltage scaling and device sizing are well understood. Pass-transistor logic: beneficial for multiplexer and XOR dominated circuits like adders, etc. Pass-transistor logic: beneficial for multiplexer and XOR dominated circuits like adders, etc. For large fanin gates, static CMOS is inefficient; a choice can be made between pseudo-nMOS, dynamic CMOS and domino CMOS. For large fanin gates, static CMOS is inefficient; a choice can be made between pseudo-nMOS, dynamic CMOS and domino CMOS.