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Dec. 1, 2005ELEC 6970-001 Class Presentation1 Impact of Pass-Transistor Logic (PTL) on Power, Delay and Area Kalyana R Kantipudi ECE Department Auburn.

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Presentation on theme: "Dec. 1, 2005ELEC 6970-001 Class Presentation1 Impact of Pass-Transistor Logic (PTL) on Power, Delay and Area Kalyana R Kantipudi ECE Department Auburn."— Presentation transcript:

1 Dec. 1, 2005ELEC 6970-001 Class Presentation1 Impact of Pass-Transistor Logic (PTL) on Power, Delay and Area Kalyana R Kantipudi ECE Department Auburn University

2 Dec. 1, 2005ELEC 6970-001 Class Presentation2 Outline: Introduction Pros & Cons of PTL A PTL Design Need for an Improved Design A Transmission gate Design A new improved PTL Design Conclusions

3 Dec. 1, 2005ELEC 6970-001 Class Presentation3 Introduction: The power equation: P total = C L V DD 2 + T sc V DD I peak + V DD I leakage P dyn = V DD 2 f clk.Σ  n.c n + V DD.ΣI sc n P leakage = V DD I subleakage = μ 0 C ox (W/L) V t 2 exp{(V GS -V TH )/nV t }

4 Dec. 1, 2005ELEC 6970-001 Class Presentation4 What Can We Reduce? Activity in the circuit Switching capacitance 1. Reducing Width and Length Supply voltage reduction Short-circuit reduction

5 Dec. 1, 2005ELEC 6970-001 Class Presentation5 What PTL Can Offer? One pass-transistor network is enough. Reduction in number of transistors. Decrease in width and length of transistors.  Results in smaller ‘input’ and ‘driving’ loads.

6 Dec. 1, 2005ELEC 6970-001 Class Presentation6 The Catch… Reduction in level of the signal (V DD -V th -IR). 1. Needs level restoration at gate outputs in order to avoid static currents. 2. Adjust threshold voltages (V thp > V thn ). Only one single path through each network must be active at a time. (To avoid shorts between the inputs) 1. A multiplexer kind of structure is to be implemented all the time.

7 Dec. 1, 2005ELEC 6970-001 Class Presentation7 PTL Logic Formulation and Implementation:

8 Dec. 1, 2005ELEC 6970-001 Class Presentation8

9 Dec. 1, 2005ELEC 6970-001 Class Presentation9 Why 250nm Instead Of 180nm Technology V DD - V Tp Volt V DD V i (t) V o (t) V Tn For 180 nm: V thn =0.51V V thp =-0.52V If a pass transistor is feeding an inverter: V in(inv) = V DD – V thn – IR drop = 1.8 – 0.51 – 0.2 = 1.09 V But for the p-transistor in an inverter to switch-OFF, the Vin should be atleast (V DD – |V thp | = 1.28 V) Other solutions: 1.Keep V thn of the NMOS pass transistors as low as possible. 2.Keep V thp of the inverter higher than V thn.

10 Dec. 1, 2005ELEC 6970-001 Class Presentation10 Trade-offs Needed Delay due to load Vs. Delay due to gate Widths of the pass transistors: 30-9-7-5-3-1

11 Dec. 1, 2005ELEC 6970-001 Class Presentation11 Trade-offs needed Delay due to load Vs. Delay due to gate Widths of the pass transistors: 30-9-7-5-3-7/3-7/7-1

12 Dec. 1, 2005ELEC 6970-001 Class Presentation12 Transmission Gate Maintains the voltage swing of the signal Strong ‘1’ and strong ‘0’. As there are two channels conducting, the device speed improves. It is found that the transmission gate has robust characteristics compared to a CMOS gate.

13 Dec. 1, 2005ELEC 6970-001 Class Presentation13 The AND Gate: CMOS AND gate: Static Power: 31.1411 pW Dynamic Power: 1.8285 uW Critical Delay: 214 pico secs. T X gate based AND: Static Power: 43.177 pW Dynamic Power: 417.863 nW Critical Delay: 172 pico secs.

14 Dec. 1, 2005ELEC 6970-001 Class Presentation14 How to get to those features: Parameters: Lpass_p/Lpass_n Wp/Lp,Wn/Ln Static Power Dynamic Power Delay in Pico secs. (1/1,9/2,5/2)59.88pW618.57nW173 (1/1,1/1,1/1)4.42uW24.01uW184 (1/1,3/1,2/1)2.67nW32.03uW145 (1/1,3/2,2/2)146.54pW368.18nW184 (1/1,6/2,3/3)43.17pW417.86nW172 (4/2,6/2,3/3)43.18pW1.07uW366 (2/2,6/2,3/3)43.18pW609.96nW260

15 Dec. 1, 2005ELEC 6970-001 Class Presentation15 Regarding the Robustness of T x Gate Gate StatusStatic PowerDynamic Power Delay in Pico secs. CMOS Without any load 31.14pW1.83uW214 Feeding an inverter 78.49pW2.14uW257.5 T x gate Without any load 43.17pW417.86nW172 Feeding an inverter 80.31pW960.32nW238.2 The T x gate based “multi_cell” implementation is in progress >>

16 Dec. 1, 2005ELEC 6970-001 Class Presentation16 A New XOR Design is Invented [4]

17 Dec. 1, 2005ELEC 6970-001 Class Presentation17 The New “multi_cell” Design [5] In this new design, the entire “Multi_cell” needs just 15 transistors. Most of the transistors will be in their minimum size. Questions: Will it work ??? Does it has the drive capability ?

18 Dec. 1, 2005ELEC 6970-001 Class Presentation18 The Waveforms

19 Dec. 1, 2005ELEC 6970-001 Class Presentation19 Circuit specifications: Circuit TypeStatic PowerDynamic PowerDelay PTL353.36pW79.24uW8.45ns CMOS356.56pW12.49uW551ps New PTL105.15pW16.63uW662ps

20 Dec. 1, 2005ELEC 6970-001 Class Presentation20 Regarding The Area Specs. CMOS has 38 transistors while the PTL has 39 transistors (most of the transistors having minimum feature size). Considering the ( Σ LW ) the area of CMOS cell is (960 □ /233 □ = 4.12) times the size of the PTL cell.

21 Dec. 1, 2005ELEC 6970-001 Class Presentation21 Conclusions: The area overhead of CMOS is at least 4 times more than the PTL. The power consumption is less in case of PTL compared to CMOS. A good PTL design needs a lot of astute trade-offs.

22 Dec. 1, 2005ELEC 6970-001 Class Presentation22 References: 1. J. M. Rabaey, A. Chandrakasan, B Nikolic, Digital Integrated Circuits-A Design Perspective. Prentice Hall, 2004. 2. R. Zimmermann and Wolfgang Fichtner, “Low-power Logic Styles: CMOS Versus Pass-Transistor Logic,” IEEE J. Solid-State Circuits, vol.32, pp. 1079-1090, Jul. 1997. 3. Geun Rae Cho, Tom Chen. "On The Impact of Technology Scaling On Mixed PTL/Static Circuits," 2002 IEEE International Conference on Computer Design (ICCD'02),p. 322, 2002. 4. Jyh-Ming Wang, Sung-Chuan Fang, Wu-Shiung Feng,“New Efficient Designs for XOR and XNOR Functions on the Transistor Level,” IEEE J. of Solid-state Circuits, Vol. 29, pp. 780-786, July 1994. 5. H. T. Bui, Y. Wang, and Y. Jiang, "Design and analysis of low-power IO-transistor full adders using novel XOR-XNOR gates," IEEE Trans. on Circuits and Systems-I/: Analog and digital signal processing, vol. 49, no. 1, pp. 25-30, Jan 2002. 6. H. Lee and G.E. Sobelman, “A new low-voltage adder circuit,” in Proc. 7th Great Lakes Symp. VLSI, Urbana, IL, 1997. 7. A. Shams and M. Bayoumi, “A new full adder cell for low-power applications,” in Proc. of the 1998 Great Lakes Symposium,1997. 8. K. Taki, “A Survey for Pass-Transistor Logic Technologies”, Proc. Asia South-Pacific Design Automation Conference, pp. 223-226, February 1998.

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