Finite State Machines Discussion D8.1 Example 36

Canonical Sequential Network State Register Combinational Network x(t) s(t+1) s(t) z(t) clk init present state input next output

Mealy Machine init s(t+1) State Register C1 next C2 s(t) present z(t) clk init present state input next C2

Moore Machine init C2 z(t) s(t+1) State Register C1 next s(t) present clk init present state input next C2

VHDL Canonical Sequential Network init Combinational Network s(t+1) s(t) State Register next state present state x(t) present input process(clk, init) present output clk z(t) process(present_state, x)

VHDL Mealy Machine process(present_state, x) init s(t+1) State Register next state s(t) present state z(t) x(t) present input process(present_state, x) clk process(clk, init)

VHDL Moore Machine init C2 z(t) s(t+1) State Register C1 next s(t) present state x(t) present input process(present_state, x) process(present_state) clk process(clk, init)

Example Detect input sequence 1101 din fsm clk dout clr din dout 1 0 1 1 0 1 1 0 1 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0

Use State Diagram Detect input sequence 1101 S1 1 1 S0 S11 CLR 1 1 S1101 1 S110 1

fsm.vhd din fsm clk dout clr

fsm.vhd clr dout din

fsm.vhd clr dout din

fsm.vhd S0 S1 S11 S110 S1101 1 CLR

fsm.vhd S0 S1 S11 S110 S1101 1 CLR

fsm.vhd clr dout din

fsmx.vhd fsmx ld(0) ld(1) din fsm dout clr ld(7) btn(3) clk btn(1) bn clk_pulse btn(0) fsmx cclk mclk clkdiv

fsmx.vhd entity fsmx is port( mclk : in STD_LOGIC; sw : in STD_LOGIC_VECTOR(7 downto 0); btn : in STD_LOGIC_VECTOR(3 downto 0); ld : out STD_LOGIC_VECTOR(7 downto 0); a_to_g : out STD_LOGIC_VECTOR(6 downto 0); dp : out STD_LOGIC; an : out STD_LOGIC_VECTOR(3 downto 0) ); end fsmx;

fsmx.vhd

fsmx.vhd component clock_pulse port( inp : in std_logic; cclk : in std_logic; clr : in std_logic; outp : out std_logic); end component; signal clr, clk, cclk, bn: std_logic; signal clkdiv: std_logic_vector(23 downto 0);

fsmx.vhd bn <= btn(1) or btn(0); clr <= btn(3); U0: clk_pulse port map (inp => bn, cclk => cclk, clr =>clr, clk => clk); U1: fsm port map (clr =>clr, clk => clk, din => btn(1), dout => ld(7)); ld(0) <= BTN(0); ld(1) <= BTN(1);

Detect input sequence 1101 Moore Machine

Mealy Machine Sequence Detector Detect 1101

Mealy State Machine

-- Example 36b: Detect 1101 with Mealy machine library IEEE; use IEEE.STD_LOGIC_1164.all; entity seqdetb is port (clk: in STD_LOGIC; clr: in STD_LOGIC; din: in STD_LOGIC; dout: out STD_LOGIC); end seqdetb; architecture seqdetb of seqdetb is type state_type is (s0, s1, s2, s3); signal present_state, next_state: state_type; begin

sreg: process(clk, clr) begin if clr = '1' then present_state <= s0; elsif clk'event and clk = '1' then present_state <= next_state; end if; end process;

C1: process(present_state, din) begin case present_state is when s0 => if din = '1' then next_state <= s1; else next_state <= s0; end if; when s1 => next_state <= s2; when s2 => if din = '0' then next_state <= s3; when s3 => when others => null; end case; end process;

Note that dout is a registered output Seq2: process(clk, clr) begin if clr = '1' then dout <= '0'; elsif clk'event and clk = '1' then if present_state = s3 and din = '1' then dout <= '1'; else end if; end process; end seqdetb; Note that dout is a registered output dout

Detect input sequence 1101 Mealy Machine