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Introduction to VHDL Multiplexers Discussion D1.1.

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1 Introduction to VHDL Multiplexers Discussion D1.1

2 Multiplexers A multiplexer is a digital switch MUX n control lines s( 0, n-1) 2 n inputs X(0, 2 n -1) 1 output, Z = X(s)

3 Multiplexers Y 4 x 1 MUX s0s1 C0 C1 C2 C3 Y s1s0 0 0 C0 0 1 C1 1 0 C2 1 1 C3

4 Multiplexers Y 4 x 1 MUX s0s1 C0 C1 C2 C3 Y s1s0 0 0 C0 0 1 C1 1 0 C2 1 1 C3 0 A multiplexer is a digital switch

5 Multiplexers Y 4 x 1 MUX s0s1 C0 C1 C2 C3 Y s1s0 0 0 C0 0 1 C1 1 0 C2 1 1 C3 0 1

6 Multiplexers Y 4 x 1 MUX s0s1 C0 C1 C2 C3 Y s1s0 0 0 C0 0 1 C1 1 0 C2 1 1 C3 1 0

7 Multiplexers Y 4 x 1 MUX s0s1 C0 C1 C2 C3 Y s1s0 0 0 C0 0 1 C1 1 0 C2 1 1 C3 1

8 A 2 x 1 MUX Behavior if (s0 = '0') then Z := A; else Z := B; end if;

9 A 4 x 1 MUX if (s0 = '0') then A := C0; B := C2; else A := C1; B := C3; end if; if (s1 = '0') then Z := A; else Z := B; end if; if (s1 = '0') then if (s0 = '0') then Z := C0; else Z := C1; end if; else if (s0 = '0') then Z := C2; else Z := C3; end if;

10 A 4 x 1 MUX case s is when "00" => Z <= C0; when "01" => Z <= C1; when "10" => Z <= C2; when others => Z <= C3; end case;

11 n-line 2-to-1 Multiplexer n-line 2 x 1 MUX a(n-1:0) b(n-1:0) y(n-1:0) sel sel y 0 a 1 b

12 library IEEE; use IEEE.std_logic_1164.all; entity mux2g is generic (width:positive); port ( a: in STD_LOGIC_VECTOR(width-1 downto 0); b: in STD_LOGIC_VECTOR(width-1 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(width-1 downto 0) ); end mux2g; An n-line 2 x 1 MUX a(n-1:0) b(n-1:0) y(n-1:0) sel n-line 2 x 1 MUX

13 library IEEE; use IEEE.std_logic_1164.all; entity mux2g is generic (width:positive); port ( a: in STD_LOGIC_VECTOR(width-1 downto 0); b: in STD_LOGIC_VECTOR(width-1 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(width-1 downto 0) ); end mux2g; Entity Each entity must begin with these library and use statements port statement defines inputs and outputs generic statement defines width of bus

14 library IEEE; use IEEE.std_logic_1164.all; entity mux2g is generic (width:positive); port ( a: in STD_LOGIC_VECTOR(width-1 downto 0); b: in STD_LOGIC_VECTOR(width-1 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(width-1 downto 0) ); end mux2g; Entity Mode: in or out Data type: STD_LOGIC, STD_LOGIC_VECTOR(width-1 downto 0);

15 Standard Logic type std_ulogic is (‘U’, -- Uninitialized ‘X’ -- Forcing unknown ‘0’ -- Forcing zero ‘1’ -- Forcing one ‘Z’ -- High impedance ‘W’ -- Weak unknown ‘L’ -- Weak zero ‘H’ -- Weak one ‘-’); -- Don’t care library IEEE; use IEEE.std_logic_1164.all;

16 Standard Logic Type std_ulogic is unresolved. Resolved signals provide a mechanism for handling the problem of multiple output signals connected to one signal. subtype std_logic is resolved std_ulogic;

17 architecture mux2g_arch of mux2g is begin mux2_1: process(a, b, sel) begin if sel = '0' then y <= a; else y <= b; end if; end process mux2_1; end mux2g_arch; Architecture a(n-1:0) b(n-1:0) y(n-1:0) sel n-line 2 x 1 MUX Note: <= is signal assignment

18 architecture mux2g_arch of mux2g is begin mux2_1: process(a, b, sel) begin if sel = '0' then y <= a; else y <= b; end if; end process mux2_1; end mux2g_arch; Architecture entity name process sensitivity list Sequential statements (if…then…else) must be in a process Note begin…end in process Note begin…end in architecture

19 library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_unsigned.all; entity Lab1 is port( SW : in STD_LOGIC_VECTOR(7 downto 0); BTN0 : in STD_LOGIC; LD : out STD_LOGIC_VECTOR(3 downto 0) ); end Lab1; Top-level design for Lab 1

20 architecture Lab1_arch of Lab1 is component mux2g generic( width : POSITIVE); port( a : in std_logic_vector((width-1) downto 0); b : in std_logic_vector((width-1) downto 0); sel : in std_logic; y : out std_logic_vector((width-1) downto 0)); end component; constant bus_width: integer := 4; begin mux2: mux2g generic map(width => bus_width) port map (a => SW(7 downto 4),b => SW(3 downto 0), sel => BTN0, y => LD); end Lab1_arch;

21 Lab1.ucf #PACE: Start of PACE I/O Pin Assignments NET "BTN0" LOC = "M13" ; NET "LD " LOC = "K12" ; NET "LD " LOC = "P14" ; NET "LD " LOC = "L12" ; NET "LD " LOC = "N14" ; NET "SW " LOC = "F12" ; NET "SW " LOC = "G12" ; NET "SW " LOC = "H14" ; NET "SW " LOC = "H13" ; NET "SW " LOC = "J14" ; NET "SW " LOC = "J13" ; NET "SW " LOC = "K14" ; NET "SW " LOC = "K13" ;

22 architecture Lab1_arch of Lab1 is component mux2g generic( width : POSITIVE); port( a : in std_logic_vector((width-1) downto 0); b : in std_logic_vector((width-1) downto 0); sel : in std_logic; y : out std_logic_vector((width-1) downto 0)); end component; constant bus_width: integer := 4; begin mux2: mux2g generic map(width => bus_width) port map (a => SW(7 downto 4),b => SW(3 downto 0), sel => BTN0, y => LD); end Lab1_arch;

23 An n-line 4 x 1 multiplexer a(n-1:0) b(n-1 :0) y(n-1 :0) sel(1:0) 8-line 4 x 1 MUX c(n-1 :0) d(n-1 :0) Sely “00”a “01”b “10”c “11”d

24 An 8-line 4 x 1 multiplexer library IEEE; use IEEE.std_logic_1164.all; entity mux4g is generic(width:positive := 8); port ( a: in STD_LOGIC_VECTOR (width-1 downto 0); b: in STD_LOGIC_VECTOR (width-1 downto 0); c: in STD_LOGIC_VECTOR (width-1 downto 0); d: in STD_LOGIC_VECTOR (width-1 downto 0); sel: in STD_LOGIC_VECTOR (1 downto 0); y: out STD_LOGIC_VECTOR (width-1 downto 0) ); end mux4g;

25 Example of case statement architecture mux4g_arch of mux4g is begin process (sel, a, b, c, d) begin case sel is when "00" => y <= a; when "01" => y <= b; when "10" => y <= c; when others => y <= d; end case; end process; end mux4g_arch; Must include ALL possibilities in case statement Note implies operator => Sely “00”a “01”b “10”c “11”d

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