MICE Readout DFPGA Firmware Progress Done Trip-t  DFPGA  AFPGA Discriminator bit map transfer control blocks done and simulated Trip-t  DFPGA  AFPGA Discriminator bit map transfer control blocks done and simulated Reading Trip-t Discriminator Bit map into DFPGA MapFIFOs with Depth control Reading Trip-t Discriminator Bit map into DFPGA MapFIFOs with Depth control Down loading the Discriminator Bit map into D-A interface FIFO on Digitise Down loading the Discriminator Bit map into D-A interface FIFO on DigitiseUnderway Add Xilinx Core Generated components Add Xilinx Core Generated components Simulate SimulateNext Add pin configuration Add pin configuration Simulate Simulate Test Test Implement L1 Data Readout Implement L1 Data Readout

Trip-t Interface DIGEN0[ U/L/B] DIGEN1[ U/L/B] TxFIFO-D MapFIFO0LMSB MapFIFO0UMSB MapFIFO0ULSB MapFIFO0LLSB Disc 0 map 16 bit MapFIFO1LMSB MapFIFO1UMSB MapFIFO1ULSB MapFIFO1LLSB MODE CTRL U/L Write Trip-t Interface D-A FPGA Interface 8 ->1 Read Select 8 bit MUXMUX PRE-RST Disc 1 map 16 bit

Trip-t Signals

DFPGA control signals