1. 1 Programming of FPGA in LiCAS ADC for Continuous Data Readout Week 7 Report Friday 15 th August 2008 Jack Hickish

2. 2 Progress Last Week Implemented error checking system – both continuous and single “get status” methods

3. 3 Since then... External FIFO Switched to using external FIFO as main buffer. Reason: it's about 100 times bigger than the internal FIFO. Could have done this from the beginning, but internal FIFO was easier to work with and simulate. But not much, in the end.

4. 4 Speed Test Test 1 Data received over USB but not written to disk. Maximum speed: 7 channels full speed (This is theoretical maximum for FPGA)‏ Test 2 Data received and written (without analysis/checking/combining bytes) to file. File closed. File reopened and overwritten with new data. Cycle continuously, checking full LED for signs of error.

5. 5 Speed Test

6. 6 Unable to do better than 1 channel at half speed – (1.4 million samples per second) or 2.8MB/s If all 16 channels were being used, this equates to 87kHz per channel. An overnight test showed 1.5 hrs error free data acquisition at this speed. However, Ian's new binary file writer is much faster (around 8 times).

7. 7 New test function implemented, which will allow data to be simulated at the earliest point in the FPGA. Allows testing of new accumulators. Simulated data is also different for each channel, can help check bits of data are not being lost to timing lags. New Test Mode

8. 8 Test everything. Make sure it all works. The Week Ahead...