SiLC Front-End Electronics LPNHE Paris March 15 th 2004

FE designs : - UCSC Time-Over Threshold based. Benefits: Simple, no ADC No analog pipe-line - Paris Shared ADC based. Benefits: Linear, true Charge data Both Very low power

SiLC Readout - Time information at one/two ends If feasible: Two fast timing channels/strip - Evaluate prototype on test bench: - Power - Shared ADC / TDC - Paris

SiLC Readout architecture Time 330 ns / 950  s ms Counter Storage Zip… Analog Pipe-line Ch. # Acquisition stage Readout and processing stage 0.18  m CMOS ADC Packing TDC PA shaper, Peak, Disc Charge, Time - Paris

UMC Deep Sub-micron CMOS 0.18  m technology - 4  s conversion time - 10 bits (500 MHz internal clock) - 40  W/ch If Preamp +ADC are running during collisions (worst case) e.g. 1/100 duty cycle and 2e6 channels Total: 150e-6 x 2e6 x 1e-2 = 3 Watts PREAMP+SHAPER  W/ch ADC POWER

Preamp Response (after 10  s shaping)

Preamp Linearity

Preamp Noise

SiLC Readout Electronics Status 03/15/04 Item Features StatusPlanned Preamp: Gain: 3.5 mV/MIP Simulated Noise: pF,  p = 10  s Dynamic range: 60 MIP Power: 51  W Shaper: Peaking time 3 –5  sGain 4 Under Design 4/04 Sample and Hold: ADC: 10 bit 4  s Comparator simulated Auto-zeroed comparator 5/04 Full ADC 128 channels in UMC 0.18 mm 6/04