1. Click to edit Master subtitle style Presented By Mythreyi Nethi HINP16C

2. Research Presentation Experiment Setup

3. Research Presentation GENERAL DESCRIPTIONS HINP16C is a 16 channel integrated circuit for use in low and intermediate energy nuclear physics. The IC was fabricated in the AMIS 0.5 µm, N-well CMOS,triple metal,double poly process. The die size was 6.47mm X 3.37 mm

4. Research Presentation Specifications 100 MeV full range with 25 keV resolution Time resolution of 500 ps for a monoenergetic 5 MeV  -particle Capable of processing either polarity Data sparsification: User selection of either hit channels or all to be read out

5. Research Presentation Channel Block Diagram

6. Research Presentation FEATURES Three gain modes: 100 MeV, 500 MeV and external pre-amplifier Capable of processing either polarity. Variable peaking time: 1 µs – 2 µs. Channel by channel disable of on-chip CFDs. Data Sparsification. Analog multiplicity output (and logical OR). Two time measurement ranges: 250 ns or 1 µs. Automatic reset of time-to-voltage and peak sampling circuits. Ability to examine the CSA, shaper and the CFD outputs.

7. Research Presentation Charge Sensitive Amplifier Every channel in the IC consists of a CSA that possesses two gain modes : 100 Mev and 500 Mev. The CSA output is split to feed energy and timing branches. The risetime is 50 ns and the falltime is 55  s. Performance Noise slope: 3 e / pF Noise at 0 pF : 600 e Noise at 75 pF: 1100 e Resolution: > 10 keV

8. Research Presentation Pulse Shaper The energy leg consists of a shaping filter with a fast return to baseline, < 20  s,. Variable peaking time: 1  s - 2  s.peaking time Energy resolution is > 25 keV in the 100 MeV mode. This pulse-shaper is followed by a continuous-time peak sampling circuit

9. Research Presentation Peak Sampler Holds the peak voltage out of the shaper. Linear to about 80 MeV. Linear Gain Amplifier Positive Peak Detector Negative Peak Detector sel Mux Peak OutInput from Shaper

10. Research Presentation Constant Fraction Discriminator (CFD) The timing leg consists of a CFD composed of a leading edge and a zero-cross discriminator.CFD The Nowlin circuits produces the bipolar pulse for the ZC.Nowlin The zero-crossing discriminator has its offsets dynamically nulled. A 6-bit DAC is used to correct offsets associated with the leading- edge circuit as well as to set CFD threshold levels. When the CFD fires it starts a time-to-voltage conversion. A fast logical ‘OR’ signal and an analog output proportional to the number of channels that were hit are available for use. CFD walk is less than 500 ps over a range of 50 dB.walk

11. Research Presentation Time-to-Voltage Converter (TVC) TVC provides the timing information about when a channel was hit relative to the other channels in the IC. TVC The TVC circuit boasts two measurement ranges: 250 ns and 1 µs. Expected time resolution on-chip is 150 ps in the 250 ns range mode.

12. Research Presentation Analog Reset Logic Provides the reset for TVC and Peak sampling circuits. Variable delay time (300 ns – 30 µs) with reference to when the CFD fires. Variable delay Automatically resets unless vetoed by the user.

13. Research Presentation Common Circuits A common channel provides biasing for the 32 processing channels and contains readout electronics.readout electronics The configuration register. The chip only responds when an externally applied chip address matches the ID stored in the chip's configuration register.

14. Research Presentation Area and Power dissipation

15. Research Presentation Results from the chip The CSA, shaper, TVC and the peak sampler seems to work fine. Configuration can be loaded perfectly. The output of the one-shot in the CFD does not produce the required result. This problem can be fixed by the FIB process.FIB process

16. Research Presentation Future Work 16 Channels 32 Channels Increase gain of the CSA.

17. Research Presentation CSA Performance

18. Research Presentation Shaper Performance

19. Research Presentation Linearity of Peak Sampler

20. Research Presentation CFD operation CFD Block Diagram

21. Research Presentation Nowlin Circuit 1 0 +1/2 1 0 0 0 -1/2 Input OUT+ OUT- Voutp = OUT+ - OUT-

22. Research Presentation CFD Walk

23. Research Presentation TVC Operation

24. Research Presentation Delay in the variable one shot

25. Research Presentation Digital circuits Hit Logic Hit0 Hit31 32 to 5 Encoder Channel Select 0 Channel Select 31 5 to 32 Decoder Encoder Output Decoder Input

26. Research Presentation Hit Logic

27. Research Presentation Configuration Bits Bit PositionFunctionDefault 00 = Enable CFD Ch 0. 1 = Disable CFD Ch 0. Ch 0 CFD enabled 10 = Enable CFD Ch 1. 1 = Disable CFD Ch 1. Ch 1 CFD enabled.................. 150 = Enable CFD Ch 15. 1 = Disable CFD Ch 15. Ch 15 CFD enabled 16 – 31Currently unused.All bits 0 320 = Positive pulses at CSA out. 1 = Negative pulses at CSA out. Negative pulses 330 = 1 µsec TVC range. 1 = 250 nsec TVC range. 1 µsec range 340 = CSA high-gain mode. 1 = CSA low-gain mode. High-gain mode 350 = test mode 1 OFF. 1 = test mode 1 ON i.e. CSA and shaper outputs for selected channel brought out to pins. CSA and shaper not brought out to pins 360 = Enable internal CSA. 1 = Select external preamp. Use internal CSA 370 = test mode 3 OFF. 1 = test mode 3 ON Peak sampling circuit of selected channel driven by external signal. Test mode 3 OFF 38 – 39Currently unused.All bits 0 40 - 47Bit 47 MS bit (8 bit ID).Chip ID = 0

28. Research Presentation Latch Design

29. Research Presentation FIB Process