1. Silicon Tracker Data Acquisition and Electronics for the Linear Collider
Jean-Francois Genat
LPNHE Universite Pierre et Marie Curie CNRS/IN2P3
On behalf of:
Philippe Bailly, Jean-Francois Genat, Herve Lebbolo,Olivier le Dortz
and Aurore Savoy Navarro
ECFA Linear Collider Workshop, Durham UK, Sept. 3d 2004

2. Output signals: very preliminary exercise
Exercise performed with 3 external layers of a Silicon tracker:
Multiplex as much as possible the output signals from the detector
At the digitization stage: highly multiplexed A/D scheme

3. The readout of the Si-tracker
- Detector occupancy:
Outer central region: Preliminary studies: < 1 %
Inner central and forward regions: Preliminary studies: < 10%  Work in progress with Geant
- Double & Multiple hit rates: Ambiguities to be estimated: tiling vs long strips
- Sparsification/pedestal substraction:  On the detector FE
- Pulse height needed: Cluster centroid to improve position resolution to 7–8µm  A 10 bit A/D under construction
- Timing information Included in the FE design. The principle & possible
performances are being studied  Paris test bench
- Digital processing for cluster algorithm and fast-track processing algorithm  Under study while designing FE
- Power dissipation studies: Present results do not anticipate a major pb  passive (or light) cooling might be achievable.
 FE Power cycling
Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d 2004

4. Context All Silicon Tracker envelope: a few 100m2, a few 106 strips
Asynchronous events: ~ 1 ms
Data taking/pre-processing ~ 200 ms
Occupancy: < a few %
Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d 2004

5. Low noise preamplifiers Long shaping time Time measurement
Goals:
Low noise preamplifiers
Long shaping time
Time measurement
Very low power dissipation
Shared ADC/TDC
sparsification
Power cycling
Compact and transparent
Choice of DSμE

6. Amplification + long shaping +
Front-end processing
S&H: digitization
Amplification + long shaping +
storage + time tagging
(To Trigger)
Calibration
Control
Charge: PA shaper, S&H, Disc
ADC
Ch #
Storage
Compaction
Time: Disc, Digital delay
Time, Charge
Counter
Readout (From Trigger)
Charge 1-45 MIP, S/N~40, Time 1ns
Technology:
Deep Sub-Micron CMOS UMC 0.18 mm
Faster and less 1/f noisy alternative: Silicon-Germanium
Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d 2004

7. Analog
N.B: The time measurement will not be included in the first FE design.
It will be first experienced on the Lab test bench.
CR-RC Shaper (3-5 us)
Sample and Hold
Input
Charge
Hold
Charge Preamp
Cf = 400 fF
Discriminators
High threshold
Digital delay
Time
Low threshold
Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d 2004

8. Deep Sub-Micron CMOS 0.18 mm technology
Preamp - Shaper
MIP
- Gain 8 mV/MIP
mW/ch
If 100 MIPS needed, just twice preamp power
Timing
Two-threshold discriminator
60 mW
ADC
- 4 ms conversion time
bits (500 MHz internal clock)
mW/ch
Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d 2004

9. Performance - Preamp + Shaper
- Noise:
- Preamp + Shaper
@ 5 ms shaping time, 50 pF detector (no leak, no bias resistor):
simulated 690 e- ENC S/N ~ 40
Gain 8mV/MIP
- Power:
- Preamp + Shaper + timing
Preamp: 85 mW Shaper: mW Timing: 60 mV
- Shared ADC/TDC
ADC: 40 mW
Total: mW/channel
Power Switching:
If Preamp –Shaper +ADC are running during collisions only:
e.g. 1/100 duty cycle and channels, then:
Total: x x = Watts only !
Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d 2004

10. Preamp Linearity 10-3 Linearity better than ± 5‰
Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d 2004

11. Shaper response Shaper response Gain: 8mV/MIP over 45 MIP 5 MIP/step
Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d 2004

12. Noise
If 1/f noise shows up at 5 ms shaping, consider Silicon-Germanium technology
Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d 2004

13. ADC Comparator: Time Walk simulations
10-4
Linearity better than ± 5‰0
Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d 2004

14. Digital - TDC counter - ADC coding - Memory
- Zero suppression and lossless data compression
- Calibration management
Tools:
Virtual Silicon Library for UMC 0.18 mm
- I/O pads
- VHDL/Verilog
- Synthesizer interface (Ambit)
Cadence Silicon Ensemble for digital layout
- Merge manually analog and digital cells
Help from Erwin Deumens at IMEC (Leuven)
Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d 2004

15. Layout 16 analog charge channels: - 60 mm pitch,
- I/O pad, preamp, shaper,
sample & hold, comparator
- Full prototype chip including digital
fits in 2.2 mm2
1mm
0.75mm
Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d 2004

16. Silicon UMC 0.18 mm Europractice (Leuven)
Standard 5 x 5 mm2 or 2.2 x 2.2 mm2 (share is possible)
One full analog channel (including I/O) pad is
60 x750mm2 = .045 mm2 only
Full 128 channels chip may fit in less than 25 mm2
(SVX4 in TSMC 0.25 is ~60 mm2 for 128 channels
including analog pipe-lines, ADC, I/O)
- Submission at Europractice: next UMC run mid October
Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d 2004

17. Emerging new VLSI technologies: - Silicon Deep Sub Micron CMOS
Conclusion
Emerging new VLSI technologies:
- Silicon Deep Sub Micron CMOS
- Silicon-Germanium alternative (incorporate DSM CMOS)
allow to implement a highly integrated front end for SiLC that does not degrade the detector resolution, both in time and amplitude within an affordable power and material budget and implement system integration such as data compaction, cluster centroid, fast tracking algorithms
Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d 2004