UC San Diego Computer Engineering. VLSI CAD Laboratory.. UC San Diego Computer EngineeringVLSI CAD Laboratory.. UC San Diego Computer EngineeringVLSI CAD Laboratory.. UC San Diego Computer EngineeringVLSI CAD Laboratory.. UC San Diego Computer EngineeringVLSI CAD Laboratory... UC San Diego Computer Engineering VLSI CAD Laboratory.. UC San Diego Computer Engineering VLSI CAD Laboratory.. UC San Diego Computer Engineering VLSI CAD Laboratory.. UC San Diego Computer Engineering VLSI CAD Laboratory.. UC San Diego Computer Engineering VLSI CAD Laboratory.. UC San Diego Computer Engineering VLSI CAD Laboratory.. UC San Diego Computer Engineering VLSI CAD Laboratory. UC San Diego Computer EngineeringVLSI CAD Laboratory.. UC San Diego Computer EngineeringVLSI CAD Laboratory.. UC San Diego Computer EngineeringVLSI CAD Laboratory.. UC San Diego Computer EngineeringVLSI CAD Laboratory.. UC San Diego Computer EngineeringVLSI CAD Laboratory. UC San Diego Computer Engineering VLSI CAD Laboratory.. UC San Diego Computer Engineering VLSI CAD Laboratory.. UC San Diego Computer Engineering VLSI CAD Laboratory.. UC San Diego Computer Engineering VLSI CAD Laboratory.. UC San Diego Computer Engineering VLSI CAD Laboratory.. UC San Diego Computer Engineering VLSI CAD Laboratory.. UC San Diego Computer Engineering VLSI CAD Laboratory. Abstract As minimum feature sizes continue to shrink, patterned features have become significantly smaller than the wavelength of light used in optical lithography. As a result, the requirement for dimensional variation control, especially in critical dimension (CD) 3sigma, has become more stringent. To meet these requirements, resolution enhancement techniques (RET) such as optical proximity correction (OPC) and phase shift mask (PSM) technology are applied. These approaches result in a substantial increase in mask costs and make the cost of ownership (COO) a key parameter in the comparison of lithography technologies. To properly calibrate the cost-benefit analysis of alternative lithography strategies, it is necessary to first understand the concept of design-aware, minimum-cost correction to achieve given parametric yield. No concept of function is injected into today's mask flow. That is, current OPC techniques are oblivious to the design intent, and the entire layout is corrected uniformly with the same effort. We propose a novel minimum cost of correction (MinCorr) methodology to determine the level of correction for each layout feature such that prescribed parametric yield is attained. We highlight potential solutions to the MinCorr problem and give a simple mapping to traditional performance optimization. We conclude with experimental results showing the achievable RET cost savings while attaining a desired level of parametric yield Trends in Mask Cost O(25 mask levels) ~ “$1M mask set” in 130nm MinCorr: The Cost of Correction Problem Many features in layout are not timing critical  more process variation may be tolerable for them Less-aggressive OPC  lower costs (reduced figure counts, shorter mask write times, higher yields) Printability of the design  a certain minimum level of OPC is required Define the selling point as the circuit delay which achieves 99% parametric yield  The MinCorr problem seeks a level of correction for each layout feature such that a prescribed selling point delay is attained with minimum total cost of corrections. Yield Aware Library Characterization Type of OPCLeff (nm) 3  of Leff Figure Count Delay ( , 3  ) for NAND2X1 Aggressive1305%5X(60.7, 2.14) Medium1306.5%4X(60.7, 2.80) No OPC13010%1X(60.7, 4.33) Conclusions and Future Work Function-aware OPC can reduce total cost of OPC while still meeting cycle time and yield constraints Can modify conventional performance optimization methods to solve the MinCorr problem; we use an off-the- shelf synthesis tool to achieve up to 77% cost reduction compared to aggressive OPC, without increasing selling point delay OPC is more of a manufacturability issue than a performance or yield issue Our ongoing research pursues: Statistical static timing analysis (SSTA) based correction flow Applying selective OPC at a finer granularity than gates: Tolerable “Edge Placement Errors” per feature can be calculated and used by the OPC tool. Alternative MinCorr solution approaches based on transistor sizing and cost based delay budgeting methods Including interconnect variation in the analysis Making the yield library input slew-aware Solving MinCorr: An Analogy to Gate Sizing Gate Sizing  MinCorr Cell Area  Cost of correction Nominal Delay  Delay (  +k  ) Cycle Time  Selling point delay Die Area  Total cost of OPC Experiments and Results DesignNormalized CostNormalized Selling Point Delay “alu128”5.0 (Aggressive OPC) (Medium OPC) (No OPC) RETs increase mask feature complexities and hence mask costs: the 130nm technology node brings on the “million-dollar mask set” The average mask set produces only 570 wafers  amortization of mask cost is difficult Mask writers work equally hard to perfect critical and non-critical shapes; errors found in either during mask inspection will cause the mask to be discarded We need Design for Value (DFV) methodology to achieve required parametric yields ($/wafer) while minimizing the total of all costs incurred Publications Y. Cao, P. Gupta, A. B. Kahng, D. Sylvester and J. Yang, “Design Sensitivities to Variability: Extrapolation and Assessments in Nanometer VLSI”, Proc. IEEE ASIC/SoC Conf., Sept. 2002, pp D. Sylvester, P. Gupta, A. B. Kahng, and J. Yang, “Toward Performance-Driven Reduction of the Cost of RET-based Lithography Control” (Invited Paper), SPIE Conf. on Design and Process Integration for Microelectronic Manufacturing, Feb. 2003, to appear. P. Gupta, A. B. Kahng, D. Sylvester and J. Yang, “A Cost-Driven Lithographic Correction Methodology Based on Off-the-Shelf Sizing Tools”, Proc. ACM/IEEE Design Automation Conf., 2003, pp Assume perfect correlation of variation along all paths  resulting linearity allows propagation of (  +3  ) or 99% delay to primary outputs using standard Static Timing Analysis (STA) tools Use off-the-shelf synthesis tool, along with yield library similar to timing libraries (e.g.,.lib) to perform OPC “sizing” operation via mapping shown at left Pessimism ensured via extreme order statistics Mask cost is assumed proportional to number of layout features Monte-Carlo simulations, coupled with linear interpolation, are used to estimate delay variance given the CD variation We generate a library similar to Synopsys.lib with (  +3  ) delay values for various output loads. We characterize for yield a subset of the Artisan TSMC 0.13  m standard-cell library. An example is given below. No OPC Aggressive OPC Synopsys Design Compiler used for synthesis Figure counts, critical dimension (CD) variations derived from Numerical Technologies OPC tool Small (4%) selling point delay variation between max- and min-corrected versions of design Sizing-based optimization achieves 65% reduction in OPC cost without sacrificing parametric yield Sample results on a 8064-gate combinational design A Cost-Driven Lithographic Correction Methodology Based on Off-the-Shelf Sizing Tools Puneet Gupta, Andrew B. Kahng Calibrating Achievable Design Annual Review September 2003