1. -1- VLSI CAD Laboratory, UC San Diego Post-Routing BEOL Layout Optimization for Improved Time- Dependent Dielectric Breakdown (TDDB) Reliability Tuck-Boon Chan and Andrew B. Kahng VLSI CAD LABORATORY, UC San Diego

2. -2- Outline TDDB Reliability TDDB Reliability Our work: reducing TDDB Margin Our work: reducing TDDB Margin –Signal-aware TDDB Analysis –Post-routing Layout Optimization Experimental Results and Conclusions Experimental Results and Conclusions

3. -3- Motivation Time-dependent dielectric breakdown (TDDB) Time-dependent dielectric breakdown (TDDB) –A dielectric forms a conductive path between the interconnects due to electrical stress  chip functional error! Breakdown time, t f α exp (-γE m ) [Zhao11] Breakdown time, t f α exp (-γE m ) [Zhao11] Electric field (E) across dielectric is increasing [ITRS2011] Electric field (E) across dielectric is increasing [ITRS2011] E increases linearly  t f reduces, TDDB risk TDDB reliability limits (1) wire density and/or (2) max. voltage

4. -4- Via-to-Wire Spacing is Critical Dielectric btw. via and wire is most susceptible to TDDB Dielectric btw. via and wire is most susceptible to TDDB Small spacing is further reduced by mask misalignment between via and wire Small spacing is further reduced by mask misalignment between via and wire Smaller spacing  higher electric field  shorter lifetime Smaller spacing  higher electric field  shorter lifetime

5. -5- Our Work (1) A chip-level TDDB reliability model A chip-level TDDB reliability model –Enable signal-aware TDDB analysis

6. -6- TDDB Model Dielectric breakdown time is modeled as a Weibull distribution [Bashir10] Dielectric breakdown time is modeled as a Weibull distribution [Bashir10] Weibull shape factor Characteristic lifetime Spacing Supply voltage F ij (t) = 1 – ( exp(-t/n ij ) β ) n ij = A  exp(- γ(V /S ij ) m ) Failure probability

7. -7- Chip Level TDDB Reliability Apply Poisson area-scaling law to estimate chip failure rate Apply Poisson area-scaling law to estimate chip failure rate S ij L ij via i wire j [Bashir10] F chip (t) = 1 – ( exp(-t  H -1    G) β ) G = Σ ij [ exp(-t   γ(V /S ij ) m ) (L ij ) 1/ β ] Stress factor: probability of interconnects being stressed α ij 

8. -8- Signal-Aware Analysis Typical TDDB analysis assumes interconnects are under “DC stress”  too pessimistic! Typical TDDB analysis assumes interconnects are under “DC stress”  too pessimistic! Obtain stress factors by running cycle-accurate logic simulation  too slow Obtain stress factors by running cycle-accurate logic simulation  too slow Proposed method: Use state probability from vector-less logic simulation  much faster Proposed method: Use state probability from vector-less logic simulation  much faster { P1 i + P1 j if (1-P1 i ) > P1 j (1-P1 i ) + (1-P1 j ) otherwise net i net j time 01 1 0 Worst-case stress ratio for a pair of state probabilities stressed α ij

9. -9- Our Work (2) Post-route layout optimization Post-route layout optimization –Shift wire edges around vias to increase via-to- wire spacing –Negligible effect on circuit timing  Does not require additional design iterations  Applicable at post-route or mask writing

10. -10- Post-Routing Layout Optimization Original Layout Design Netlists State probability Layout optimization Modified layout Signal-aware analysis (optional) Inputs TDDB analysis and layout optimization flow Calculate TDDB reliability Original layout + Marker layers Alternative layout implementation

11. -11- Defining Segments for Perturbation via wire TDDB critical region Shift this edge to increase spacing Shift this edge to preserve wire width Define movable edges for layout optimization Overlapped region

12. -12- Shifting Wire Edges Shift wire edge to increase via-to-wire spacing Shift wire edge to increase via-to-wire spacing Shifting is not applied if it violates via enclosure rule Shifting is not applied if it violates via enclosure rule

13. -13- Experiment Setup 4 Benchmark circuits 4 Benchmark circuits Synopsys 32nm library Synopsys 32nm library 160nm metal pitch 160nm metal pitch Analyze TDDB on M2, M3 & M4 Analyze TDDB on M2, M3 & M4 Layout ParametersValuesTDDB Model Parameters Values Min. wire spacing80nmβ1.0 Min. wire width80nm ɣ 49 (nm/V) 0.5 Min. via-to-wire spacing80nmm0.5 Via width70nmV1.0V Via-to-wire spacing variation5nmH1.6 х 10 19 s  nm Max. wire edge shift4nm (5%) Wire segment width95nm

14. -14- Layout Optimization Results Layout optimization  ~110% lifetime Layout optimization  ~110% lifetime Signal-aware analysis  ~200% lifetime Signal-aware analysis  ~200% lifetime

15. -15- Timing Impact of Layout Optimization Total nets Opt. nets Δ Res. (Ω) Δ Cap. (fF) Gate-wost Δ Delay (ps) Wire-worst Δ Delay (ps) Max. Avg.Max.Avg. AES14k8.0k0.0880.0460.7930.0170.9690.018 JPEG29k9.4k0.1430.0830.6150.0070.6000.007 MPEG210k3.4k0.1440.0561.5780.0121.5800.012 SPARC_ECU15k7.0k0.2460.0760.6490.0111.0900.011 Average17k7k0.1550.0650.9090.0121.0600.012 40% of nets are modified 40% of nets are modified ΔR per net < 0.3 Ω, ΔC per net < 0.1 fF, ΔR per net < 0.3 Ω, ΔC per net < 0.1 fF, Average gate-worst Δdelay = 0.012ps, Average gate-worst Δdelay = 0.012ps, –Add total ΔC at driver’s output pin Average wire-worst Δdelay = 0.012ps Average wire-worst Δdelay = 0.012ps –Add total ΔC at receivers’ input pin –Add total ΔR at driver’s output pin

16. -16- Conclusions TDDB is a reliability issue for BEOL TDDB is a reliability issue for BEOL –Limits pitch scaling and/or supply voltage Signal-aware TDDB analysis  2X chip lifetime Signal-aware TDDB analysis  2X chip lifetime Post-routing layout optimization  +10% chip lifetime with negligible impact on timing Post-routing layout optimization  +10% chip lifetime with negligible impact on timing

17. -17- Thank you!

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