Lucas-Lehmer Primality Tester Presentation 4 February 15, 2006 Team: W-4 Nathan Stohs W4-1 Brian Johnson W4-2 Joe Hurley W4-3 Marques Johnson W4-4 Design Manager: Prateek Goenka Overall Objective: The Testing of Prime numbers

Status Finished –Project Chosen –C simulations –Behavioral Verilog –Structural Verilog –Revised Floor Plan –Schematics ( 90%) In Progress –Simulation of Schematics To Do –Simulations –Layout

Design Decisions Current Implementation: –Ripple Carry Adder –Serial Mod Multiplier –Barrel Shifter Future: –Carry End Around Adder

Modulo Multiply (2 n -1) Has to do with partial products The algorithm calls for a Mod every time that there is a chance Example: Mod X Leave Mod

Simulation Results Fully simulates Mersenne Primes up to 30 Using the algorithm below Numbers above 2 30 make the code overflow because of the squaring in the algorithm 2 P -1 is prime if and only if S p-2 is zero in this sequence: S 0 = 4, S N = (S N ) mod (2 P -1) S 0 = 4 S 1 = (4 * 4) mod = 14 S 2 = (14 * 14) mod = 67 S 3 = (67 * 67) mod = 42 S 4 = (42 * 42) mod = 111 S 5 = (111 * 111) mod = 0 So for : Result says it is prime

Reg:P Mod Calc Mod Serial Multiplier Counter 0:P-2 Comparator Counter = P-2 Check 0 Block Diagram P Out 16 1 FSM 16 start 1 done

Mod Serial Multiplier Block Diagram Mod add Register 2 p Sub 2 16 Next Partial Product FSM 16

Simulation of Mod Add x=68, y=128 P=7, mod by 127 x+y = mod 127 = 69

Schematic for Mod Add

What we have completed Moduleschematicsimulation Registersyesno mod calcyesno counteryesno compareyesno check zeroyesno fsmno top levelno partial productyesno mod addyes sub 2yes

Transistor Counts ModuleTransistor Count FSM300 Mod Calc2440 Counter1656 Mod Multiply15302 Registers1848 Compare for zero92 Total21638

Block Area Estimates ModuleArea (μm 2 ) FSM900 Mod Calc3500 Counter6000 Mod Multiply75000 Registers3000 Compare for zero300 Total88300

Floorplan

What’s Next Possibly modify design so that prime logic can be turned off Continue optimizing –Modify our modules, removing unnecessary logic Analyze power/size tradeoffs between adders Finish up on the schematic Do the layout

Questions?