E-Voting Machine - Design Presentation Group M1 Bohyun Jessica Kim Jonathan Chiang Chi Ho Yoon Donald Cober Mon. Sept 29 System Hardware Component Diagram Gate-level Data path Updated Transistor Estimates Floorplan Secure Electronic Voting Terminal

Floor plan -COMMS block detail -User ID SRAM block detail -Aspect ratio of each blocks Structural Verilog – Finish by this Friday Coming up – Layout smaller blocks (COMMS, User ID SRAM, etc) Status Update

COMMS block details COMMS – using bit slice – About 1:6 per slice – Total chip 8:6  4:3 aspect ratio – Have 16 bits of input and output data going bidirectional horizontally – Key 32 bits going bidirectional vertically Design decision: combine Key register, Comms Reg, Comms main logic, and shift I/O 1 1 ½ 1 ¼ ¼ 1 1 ½ 1 REG MUX ADD XOR XOR ADD REG MUX REG Key register COMMS REG COMMS main logic Shift InShift Out

User ID SRAM block details Total 454 transistors = 8 bits by 8 address lines Aspect ratio of 1:1 3 bits address line = 8 address line 8 bits of data

Finally… the Floor Plan COMMS (Key Reg, COMMS Reg, Shift I/O) KEY SRAM F S M’s USER ID SRAM Choice SRAM TX check Selection Counter USER INPUT Message ROM Write-In SRAM Aspect ratio Based on User ID SRAM 107 by 69 Approx. 5:3 aspect ratio Data Bus 12

Questions? Thank you!