Logic Values 0:logic 0 / false 1:logic 1 / true X:unknown logic value Z:high-impedance

Strength levels Strength levelTypeDegree supplyDrivingstrongest strongDriving pullDriving largeStorage weakDriving mediumStorage smallStorage highzHigh Impedanceweakest

Data Types Nets Connects between hardware elements Must be continuously driven by Continuous assignment (assign) Module or gate instantiation (output ports) Default initial value for a wire is “ Z ” (and for a trireg is “ x ” ) Registers Represent data storage elements Retain value until another value is placed on to them Similar to “ variables ” in other high level language Different to edge-triggered flip-flop in real ciucuits Do not need clock Default initial value for a reg is “ X ”

Examples reg a; // a scalar register wand w; // a scalar net of type “ wire and ” reg [3:0] v; // a 4-bit vector register from msb to lsb reg [7:0] m, n; // two 8-bit registers tri [15:0] busa; // a 16-bit tri-state bus wire [0:31] w1, w2; // Two 32-bit wires with msb being the 0 bit, not recommended

Net Types The most common and important net types wire and tri for standard interconnection wires wire: single driver e.g. output of “ and ” gate tri: multiple driver e.g. multiplexer supply1 and supply0  “ x ” strong1 and supply1  “ supply1 ”

Net Types Other wire types wand, wor, triand, and trior for multiple drivers that are wired-anded and wired-ored tri0 and tri1 pull down and pull up trireg for net with capacitive storage If all drivers at z, previous value is retained Two states: Driven state: at least one driver drives 0, 1, x Capacitive state: all driver have high impedance “ z ” Strength: small, medium, large; default is medium

An example for wire, tri0, tri1 module tritest(); wire w1, w2, w3, w4; tri0 t01, t02, t03, t04; tri1 t11, t12, t13, t14; assign w1 = 0; assign t01 = 0; assign t11 = 0; assign w2 = 1'bz; assign t02 = 1'bz; assign t12 = 1'bz; assign w3 = 1; assign t03 = 1; assign t13 = 1; Initial begin #1;$display(w1, w2, w3, w4); $display(t01, t02, t03, t04); $display(t11, t12, t13, t14); end endmodule Results: 0 z 1 z

Register Types reg any size, unsigned Integer integet a,b; // declaration 32-bit signed (2 ’ s complement) Time 64-bit unsigned, behaves like a 64-bit reg $display( “ At %t, value=%d ”,$time,val_now) real real c,d; //declaration 64-bit real number Defaults to an initial value of 0

Numbers & Negative Numbers Constant numbers are integer or real constants. Integer constants are written as “ width ‘ radix value ” The radix indicates the type of number Decimal (d or D) Hex (h or H) Octal (o or O) Binary (b or B) A number may be sized or unsized

Number Specification (continue) Sized numbers ’ is in decimal and specifies the number of bits ‘ is: ‘d ‘D ‘h ‘H ‘b ‘B ‘o ‘O The digits are 0-f, uppercase may be used Examples: 4’b ’habc 16’d255

Number Specification Unsized numbers – The is not specified (default is simulator/compiler specific, >= 32 bits) Numbers without a base are decimal by default Examples 100 // Decimal 100, 32 bits by default 6’h3a // Binary ’bx // One-bit X 32’bz // 32 bits of High-Z (impedance)

Operators

Example assign A1 = (3+2) %2; // A1 = 1 assign A2 = 4 >> 1; assign A4 = 1 << 2; // A2 = 2 A4 = 4 assign Ax = (1= =1'bx); //Ax=x assign Bx = (1'bx!=1'bz); //Bx=x assign D0 = (1= =0); //D0=False assign D1 = (1= =1); //D1=True assign E0 = (1= = =1'bx); //E0=False assign E1 = (4'b01xz = = = 4'b01xz);; //E1=True assign F1 = (4'bxxxx = = = 4'bxxxx); //F1= True assign x = a ? b : c //if (a) then x = b else x = c

Concatenation operator // A=1 ’ b1; B=2 ’ b00, C=2 ’ b10; D=3 ’ b110; Y={B, C} //Result Y is 4 ’ b0010 Y={A, B, C, D, 3 ’ b001} //Result Y is 11 ’ b Y={A, B[0], C[1]} // Result Y is 3 ’ b101

Replication operator Reg A; Reg [1:0] B, C; Reg [2:0] D; A=1 ’ b1; B=2 ’ b00, C=2 ’ b10; D=3 ’ b110; Y={4{A}} // Result Y is 4 ’ b1111 Y={4{A}, 2{B}} // Result Y is 8 ’ b Y ={4{A}, 2{B}, C} //Result Y is 8 ’ b

Example – Multiplexer_1 // Verilog code for Multiplexer implementation using assign // File name: mux1.v // by Harsha Perla for // // Available at module mux1( select, d, q ); input [1:0] select; input [3:0] d; output q; wire q; wire[1:0] select; wire[3:0] d; assign q = d[select];

Example – Multiplexer_2 // Verilog code for Multiplexer implementation using always block. // by Harsha Perla for // // Available at module mux2( select, d, q ); input[1:0] select; input[3:0] d; output q; reg q; wire[1:0] select; wire[3:0] d; or select) q = d[select]; endmodule

Example – Multiplexer_3 module mux4_1 (out, in0, in1, in2, in3, sel) ; output out ; input in0,in1,in2,in3 ; input [1:0] sel ; assign out = (sel == 2'b00) ? in0 : (sel == 2'b01) ? in1 : (sel == 2'b10) ? in2 : (sel == 2'b11) ? in3 : 1'bx ; endmodule

Exercise Design an 1-to-8 Demultiplexer