1. For NTUEE Undergraduate
Verilog HDL Overview
Prof. An-Yeu Wu
Date:2002/05/17
For NTUEE Undergraduate
VLSI Design Course

2. OUTLINE Introduction Basics of the Verilog Language
Gate-level modeling
Data-flow modeling
Behavioral modeling
Simulation and test bench
A. Y. Wu

3. What is Verilog HDL ? Hardware Description Language
Mixed level modeling
Behavioral
Algorithmic ( like high level language)
Register transfer (Synthesizable)
Structural
Gate (AND, OR ……)
Switch (PMOS, NOMS, JFET ……)
Single language for design and simulation
Built-in primitives and logic functions
User-defined primitives
Built-in data types
High-level programming constructs
A. Y. Wu

4. OUTLINE Introduction Basics of the Verilog Language
Overview of Verilog Module
Identifier & Keywords
Logic Values
Data Types
Numbers & Negative Numbers
Gate-level modeling
Data-flow modeling
Behavioral modeling
Simulation and test bench
A. Y. Wu

5. Overview of Verilog Module
Test bench
A. Y. Wu

6. module functionality or structure
Basic unit --Module
module module_name (port_name);
port declaration
data type declaration
module functionality or structure
endmodule
A. Y. Wu

7. Latch Q=D․clk+ clk_b․Q Q_b=D_b․clk+clk_b․Q_b
module Latch ( Q,Q_b,D,D_b,clk );
//port declaration
output Q,Q_b;
input D,D_b,clk ;
reg Q,Q_b;
or D_b or clk or
Q_b or Q)
begin
Q=(D&clk)|(~clk&Q);
Q_b=D_b&clk|~clk&Q_b;
end
endmodule
Q=D․clk+ clk_b․Q
Q_b=D_b․clk+clk_b․Q_b
A. Y. Wu

8. Register / Flip-flop Sub-module module D_register(q,d1,clk);
input d1,clk;
output q;
wire d1_b, clk_b;
assign d1_b=~d1;
assign clk_b=~clk;
dff dff1(d,d_b,d1,d1_b,clk_b),
dff2(q_b,q,d_b,d,clk);
endmodule
Sub-module
dff ( Q,Q_b,D,D_b,clk );
A. Y. Wu

9. Instances module adder8(....) ; adder add1(a,b,1’b0,s1,c1) ,
module adder (in1,in2,cin,sum,cout);
endmodule
module adder8(....) ;
adder add1(a,b,1’b0,s1,c1) ,
add2(.in1(a2),.in2(b2),.cin(c1),.sum(s2)
,.cout(c2)) ;
.....
endmodule
Mapping port positions
Mapping names
A. Y. Wu

10. Identifier & Keywords Identifier Keywords
User-provided names for Verilog objects in the descriptions
Legal characters are “a-z”, “A-Z”, “0-9”, “_”, and “$”
First character has to be a letter or an “_”
Example: Count, _R2D2, FIVE$
Keywords
Predefined identifiers to define the language constructs
All keywords are defined in lower case
Cannot be used as identifiers
Example:initial, assign, module, always….
A. Y. Wu

11. Logic Values 0:logic 0 / false 1:logic 1 / true X:unknown logic value
Z:high-impedance
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12. Data Types Nets ( wire or reg (in combinational always block)
Connects between structural elements
Must be continuously driven by
Continuous assignment (assign)
Module or gate instantiation (output ports)
Default initial value for a wire is “Z”
Registers ( reg (in sequential always block) )
Represent abstract data storage elements
Updated at an edge trigger event and holds its value until another edge trigger event happens
Default initial value for a wire is “X”
A. Y. Wu

13. Examples reg a; // a scalar register
wand w; // a scalar net of type “wire and”
reg [3:0] v; // a 4-bit vector register/wire from msb to lsb
reg [7:0] m, n; // two 8-bit registers/wire
tri [15:0] busa; // a 16-bit tri-state bus
wire [0:31] w1, w2;
// Two 32-bit wires with msb being the 0 bit, not recommended
A. Y. Wu

14. Net Types The most common and important net types Other wire types
wire and tri
for standard interconnection wires
supply 1 and supply 0
Other wire types
wand, wor, triand, and trior
for multiple drivers that are wired-anded and wired-ored
tri0 and tri1
pull down and pull up
trireg
for net with capacitive storage
If all drivers at z, previous value is retained
A. Y. Wu

15. Register Types reg Integer (not synthesizable)
any size, unsigned
Integer (not synthesizable)
integet a,b; // declaration
32-bit signed (2’s complement)
Time (not synthesizable)
64-bit unsigned, behaves like a 64-bit reg
$display(“At %t, value=%d”,$time,val_now)
real, realtime (not synthesizable)
real c,d; //declaration
64-bit real number
Defaults to an initial value of 0
A. Y. Wu

16. Numbers & Negative Numbers
Constant numbers are integer or real constants. Integer constants are written as “width ‘radix value”
The radix indicates the type of number
Decimal (d or D)
Hex (h or H)
Octal (o or O)
Binary (b or B)
A number may be sized (two’s complement) or unsized
Ex: h12_unsized = ‘h12; h12_sized = 6’h12;
Ex: PA = -12, PB = -’D12, PC= -32’D12;
A. Y. Wu

17. Operators
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18. Example assign A1 = (3+2) %2; A1 = 1
assign A2 = 4 >> 1; assign A4 = 1 >> 2;
A2 = 2 A4 = 4
assign Ax = (1= =1'bx);
assign Bx = (1'bx!=1'bz);
assign D0 = (1= =0); assign D1 = (1= =1);
assign E0 = (1= = =1'bx); E0 = 0; False
assign E1 = 4'b01xz = = = 4'b01xz; E1 = 1; True
assign F1 = (4'bxxxx = = = 4'bxxxx); F1 = 1; True
assign x = a ? b : c if (a) then x = b else x = c
A. Y. Wu

19. OUTLINE Introduction Basics of the Verilog Language
Gate-level modeling
Data-flow modeling
Behavioral modeling
Simulation and test bench
A. Y. Wu

20. Gate-level modeling(1)
The following gates are built-in types in the simulator
and, nand, nor, or, xor, xnor
First terminal is output, followed by inputs
and a1 (out1, in1, in2);
nand a2 (out2, in21, in22, in23, in24);
buf, not
One or more outputs first, followed by one input
not N1 (OUT1, OUT2, OUT3, OUT4, INA);
buf B1 (BO1, BIN);
A. Y. Wu

21. Gate-level modeling(2)
bufif0, bufif1, notif0, notif1: three-state drivers
Output terminal first, then input, then control
bufif1 BF1 (OUTA,INA,CTRLA);
pullup, pulldown
Put 1 or 0 on all terminals
pullup PUP (PWRA, PWRB, PWRC);
Instance names are optional
ex: not (QBAR, Q)
A. Y. Wu

22. Example module MUX4x1 (Z, D0, D1, D2, D3, S0, S1); output Z;
input D0, D1, D2, D3, S0, S1;
and (T0, D0, S0BAR, S1BAR);
(T1, D1, S0BAR, S1),
(T2, D2, S0, S1BAR),
(T3, D3, S0, S1);
not (S0BAR, S0), (S1BAR, S1);
nor (Z, T0, T1, T2, T3);
endmodule
4 X 1 multiplexer circuit
A. Y. Wu

23. OUTLINE Introduction Basics of the Verilog Language
Gate-level modeling
Data-flow modeling
Behavioral modeling
Simulation and test bench
A. Y. Wu

24. Data-flow modeling(1) Models behavior of combinational logic
Assign a value to a net using continuous assignment
Examples:
wire [3:0] Z, PRESET, CLEAR;
assign Z = PRESET & CLEAR;
wire COUT, CIN;
wire [3:0] SUM, A, B;
assign {COUT, SUM} = A + B + CIN;
A. Y. Wu

25. Data-flow modeling(2) Left-hand side (target) expression can be:
Single net (ex: Z)
Part-select (ex: SUM[2:0])
Bit-select (ex: Z[1])
Concatenation of both (ex: {COUT, SUM[3:0]})
Expression on right-hand side is evaluated whenever any operand value changes
Note: Concatenation example
{A,1’b0} -> x2
{A,2’b0} -> x4
wire [7:0]A,B; wire [16:0]C; assign C={A,B};
A. Y. Wu

26. Delay Delay between assignment of right-hand side to left-hand side
assign #6 ASK = QUIET || LATE; //Continuous delay
Netdelay
wire #5 ARB;
// Any change to ARB is delayed 5 time units before it takes effect
If value changes before it has a chance to propagate, latest value change will be applied – Inertial delay
A. Y. Wu

27. OUTLINE Introduction Basics of the Verilog Language
Gate-level modeling
Data-flow modeling
Behavioral modeling
Simulation and test bench
A. Y. Wu

28. Behavioral modeling Procedural blocks:
initial block: executes only once
always block:executes in a loop
Block execution is triggered based on user-specified conditions
(posedge clk) ………
All procedural blocks are automatically activated at time 0
All procedural blocks are executed concurrently
reg is the main data type that is manipulated within a sequential block
It holds its value until assigned a new value
A. Y. Wu

29. Initial Statement Executes only once at the beginning of simulation
statements
Used for initialization and waveform generation
//Initialization:
reg [7:0] RAM[0:1023];
reg RIB_REG;
initial begin
integer INX;
RIB_REG =0;
for (INX = 0; INX < 1024; INX = INX + 1)
RAM[INX] = 0;
end
group
multiple
statements
A. Y. Wu

30. Always Statement(1)
Executes continuously; must be used with some form of timing control
always (timing_control) always
statements CLK = ~CLK
// Will loop indefinitely
Four forms of event expressions are often used
An OR of several identifiers (comb/seq logic)
The rising edge of a identifier (for clock signal of a register)
The falling edge of a identifier (for clock signal of a register)
Delay control (for waveform generator)
A. Y. Wu

31. Always Statement(2)
Any number of initial and always statements may appear within a module
Initial and always statements are all executed in parallel
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32. Example module example (D, CURRENT_STATE, Q, NEXT_STATE);
input D, CURRENT_STATE;
output Q, NEXT_STATE;
reg CLK, Q, NEXT_STATE;
always #5 CLK = ~CLK;
CLK)
begin
Q =D;
end
CLK)
NEXT_STATE = CURRENT_STATE;
endmodule
delay-controlled always block
clock period = 10
activated when CLK has
a 0 -> 1 transition
activated when CLK has
a 1 -> 0 transition
A. Y. Wu

33. Procedural Assignments
The assignment statements that can be used inside an always or initial block
The target must be a register or integer type
or B) // infer wire
begin
B = A;
C = B;
end // C=A
CLK) // infer flip-flop
B <= A;
C <= B;
D <= C;
end // Clock skew!!
A. Y. Wu

34. Conditional Statements
if and else if statements
if (expression)
statements
{ else if (expression)
statements }
[ else
statements ]
if (total < 60) begin
grade = C;
total_C = total_C + 1;
end
else if (sum < 75) begin
grade = B;
total_B = total_B + 1;
else grade = A;
case statement
case (case_expression)
case_item_expression
{, case_item_expression }:
statements ……
[ default: statements ]
endcase
case (OP_CODE)
2`b10: Z = A + B;
2`b11: Z = A – B;
2`b01: Z = A * B;
2`b00: Z = A / B;
default: Z = 2`bx;
A. Y. Wu

35. Loop Statements Four loop statements are supported
The for loop
The while loop
The repeat loop
The forever loop
The syntax of loop statements is very similar to that in C language
Most of the loop statements are not synthe-sizable in current commercial synthesizers
A. Y. Wu

36. OUTLINE Introduction Basics of the Verilog Language
Gate-level modeling
Data-flow modeling
Behavioral modeling
Simulation and test bench
A. Y. Wu

37. Simulation and test bench(1)
Design, stimulus, control, saving responses, and verification can be completed in a single language
Stimulus and control
Use initial procedural block
Saving responses
Save on change
Display data
Verification
Automatic compares with expected responses
A. Y. Wu

38. Simulation and test bench(2)
The behavior of a design can be simulated by HDL simulators
Test benches are given by users as the inputs of the design
Some popular simulators
Verilog-XL (Cadence TM , direct-translate simulator)
NC-Verilog (Cadence TM , compiled-code simulator)
VCS (ViewLogic TM , compiled-code simulator)
A. Y. Wu

39. Supports for Verification
Verilog provides a number of system tasks and system functions.
$time is a system function that returns the current simulation time.
$monitor is a system task that displays the values of the argument list whenever any of the arguments change.
Examples:
$monitor($time,,out,,a,,b,,sel);
$monitor($time,”%b %h %d %o, sig1,sig2,sig3,sig4);
A. Y. Wu

40. Test Bench
module test_bench;
data type declaration
module instantiation
applying stimulus
display results
endmodule
A test bench is a top level module without inputs and outputs
Data type declaration
Declare storage elements to store the test patterns
Module instantiation
Instantiate pre-defined modules in current scope
Connect their I/O ports to other devices
Applying stimulus
Describe stimulus by behavior modeling
Display results
By text output, graphic output, or waveform display tools
A. Y. Wu

41. Example module testfixture; reg [15:0] a,b,ci; wire [15:0] sum;
wire cout;
adder adder0(sum,cout,a,b,ci);
initial begin
a=0;b=0;ci=0;
#10 ci=1; #10 ci=0; b=1;
#10 ci=1; a=1;
#10 $finish;
end
Initial $monitor ($time,” sum= %b cout= %b a= %b b= %b
ci=%b”,sum,cout,a,b,ci);
endmodule
data type declaration
module instantiation
applying stimulus
display results
A. Y. Wu