1. Chap. 3 Basic Concepts

2. 2 Basic Concepts Lexical Conventions Data Types System Tasks and Compiler Directives Summary

3. 3 Lexical Conventions - I Whitespace  Blank space (\b)  Tabs (\t)  Newlines (\n) Comments  //: single line  /* … */ : multiple line Operators  Unary: ~ 、 !  Binary: + 、 - 、 &&  Ternary: a = b ? c : d;

4. 4 Lexical Conventions - II Number Specification  Sized numbers: ’ 4’b1111 12’habc 16’d255  Unsized numbers 23456 ‘hc3 ‘o21  X (unknown) and Z (high impedance) 12’h13x 6’hx 32’bz  Negative numbers -8’d3  Underscore characters and Question marks 12’b1111_0000_1010 equals to 12’b111100001010 4’b10?? equals to 4’b10zz

5. 5 Lexical Conventions - III String  “Hello Verilog World”  “a/b” Identifiers and Keywords  reg value;  input clk;

6. 6 Basic Concepts Lexical Conventions Data Types System Tasks and Compiler Directives Summary

7. 7 Data Types Value set and strength Nets Registers Vectors Integer 、 Real and Time Register Data Types Arrays Memories Parameters Strings

8. 8 Value Set and Strength

9. 9 a, b, c are wires (nets). Nets Declare a physical wire Keyword: wire 、 wand 、 wor 、 tri 、 trior 、 trireg  wire a;  wire b, c;  wire d = 1’b0;

10. 10 Registers Storage element for data Do not equal to “hardware register” Similar to variables in C reg reset; initial begin reset = 1’b1; #100 reset = 1’b0; end

11. 11 Vectors - I wire and register can be defined as “vector” form format  [high#:low#] or [low#:high#] wre a; wire [7:0] bus; wire [31:0] busA, busB, busC; reg clock; reg [0:40] virtual_addr;

12. 12 Vectors - II Subset of vector  Partial bits of vector busA[7] Bus[2:0] Virtual_addr[0:1]

13. 13 Vectors - III Fixed width subset  [ +:width] or [ -:width] reg [255:0] data1; reg [0:255] data2; reg [7:0] byte; byte = data1[31-:8]; // data1[31:24] byte = data1[24+:8]; // data1[31:24] byte = data2[31-:8]; // data2[24:31] byte = data2[24+:8]; // data2[24:31] for (j=0; j<=31; j=j+1) // [7:0], [15:8]…[255:248] byte = data[(j*8)+:8]; data1[(byteNum*8)+:8] = 8’b0;

14. 14 Integer, Real, and Time Register Data Types – I Integer can represent “signed” number Real integer counter; initial counter = -1; real dalta; initial begin delta = 4e10; delta = 2.13; end integer i; initial i = delta; // rounded value of 2.13

15. 15 Integer, Real, and Time Register Data Types – II Time  Storing simulation time time save_sim_time; initial save_sim_time = $time;

16. 16 Arrays - I Type: integer, register, time, real, or vector. Dimension: no limit, but dimension must be constant Format  [ ] integer count[0:7]; reg bool[31:0]; time chk_point[1:100]; reg [4:0] port_id[0:7]; integer matrix[4:0][0:255]; reg [63:0] array_4d [15:0][7:0][7:0][255:0]; wire [7:0] w_array2 [5:0]; wire w_array1[7:0][5:0];

17. 17 Array - II count[5] = 0; chk_point[100] = 0; port_id[3] = 0; matrix[1][0] = 33559; araay_4d[0][0][0][0][15:0] = 0;fff port_id = 0; // error usage matrix[1] = 0; // error usage

18. 18 Memories Array of register reg mem1bit [0:1023]; reg [7:0] membyte [0:1023]; membyte[511]

19. 19 Parameters Define a constant Can be re-defined at topper level using “defparam” localparam (Verilog 2001 new feature)  Can not be re-defined by “defparam” parameter port_id = 5; parameter cache_line_width = 256; parameter signed [15:0] WIDTH;

20. 20 Strings Can be assigned to register reg [8*18:1] string_value; initial string_value = “Hello Verilog World”;

21. 21 表 3-3 特殊字元

22. 22 Basic Concepts Lexical Conventions Data Types System Tasks and Compiler Directives Summary

23. 23 System Tasks Displaying information Monitoring information Stopping and finishing

24. 24 Displaying information - I $display (p1, p2, p3,…, pn);  Like “printf” in C  Format specification list

25. 25 Displaying information - II

26. 26 Displaying information - III

27. 27 Displaying information - IV

28. 28 Monitoring Information $monitor(p1,p2,…, pn);  Monitor signal change and output the change

29. 29 Stopping and finishing $stop: stop simulation and enter interactive mode to debug $finish: end of simulation

30. 30 Compiler Directives `define  Define text macro, like #define in C `include  Include the context of another file, like #include in C

31. 31 Usage of `define

32. 32 Usage of `include

33. 33 Basic Concepts Lexical Conventions Data Types System Tasks and Compiler Directives Summary

34. 34 Summary Verilog is similar to C Lexical conventions Data Types  Value set, wire, register, vector, integer, real, time, array, memory, parameter, string… System Tasks  $display, $monitor, $stop, $finish Compiler Directives  `define and `include