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Chapter 3: Dataflow Modeling

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Presentation on theme: "Chapter 3: Dataflow Modeling"— Presentation transcript:

1 Chapter 3: Dataflow Modeling
Prof. Ming-Bo Lin Department of Electronic Engineering National Taiwan University of Science and Technology

2 Syllabus Objectives Dataflow modeling Operands Operators

3 Objectives After completing this chapter, you will be able to:
Describe what is the dataflow modeling Describe how to use continuous assignments Describe how to specify delays in continuous assignments Describe the data types allowed in Verilog HDL Describe the operation of the operators used in Verilog HDL Describe the operands may be used associated with a specified operator

4 Syllabus Objectives Dataflow modeling Operands Operators Introduction
Continuous assignment Expressions Delays Operands Operators

5 Why Dataflow ? Any digital system interconnecting registers
combinational logic circuits

6 Features of Dataflow A powerful way to implement a design
Logic synthesis tools can be used to create a gate-level netlist RTL (register transfer level) is a combination of dataflow and behavioral modeling

7 Syllabus Objectives Dataflow modeling Operands Operators Introduction
Continuous assignment Expressions Delays Operands Operators

8 Basic Statements Continuous assignments Variations
Net declaration assignments Implicit net declarations

9 Continuous Assignments
Syntax assign [delay] net_lvalue = expression; assign [delay] net1_lvalue = expr1, [delay] net2_lvalue = expr2, ..., [delay] netn_lvalue = exprn; assign #5 {c_out, sum[3:0]} = a[3:0] + b[3:0] + c_in;

10 Net Declaration Assignments
Only one net declaration assignment per net wire out; // regular continuous assignment assign out = in1 & in2; wire out = in1 & in2; // net declaration assignment

11 Implicit Net Declarations
A feature of Verilog HDL wire in1, in2; assign out = in1 & in2;

12 Syllabus Objectives Dataflow modeling Operands Operators Introduction
Continuous assignment Expressions Delays Operands Operators

13 Expressions expression = operators + operands Operators Operands

14 Operators

15 Operands constants parameters nets
variables (reg, integer, time, real, realtime) bit-select part-sel array element function calls

16 Syllabus Objectives Dataflow modeling Operands Operators Introduction
Continuous assignment Expressions Delays Operands Operators

17 Three Ways of Specifying Delays
Regular assignment delay Net declaration assignment delay Net declaration delay

18 Regular Assignment Delays
The inertial delay model is defaulted wire in1, in2, out; assign #10 out = in1 & in2;

19 Net Declaration Assignment Delays
To specify both the delay and assignment on the net The inertial delay model is defaulted // net declaration assignment delay wire #10 out = in1 & in2; // regular assignment delay wire out; assign #10 out = in1 & in2;

20 Net Declaration Delays
Associate a delay value with a net declaration // net delays wire #10 out; assign out = in1 & in2; // regular assignment delay wire out; assign #10 out = in1 & in2;

21 Syllabus Objectives Dataflow modeling Operands Operators Constants
Data types Operators

22 Types of Constants integer real string

23 Integer Constants -123 Simple decimal form Base format notation
12345 Base format notation 16’habcd 2009 4’sb1001 // -7

24 Real Constants Decimal notation Scientific notation 1.5 //
1.5 // .3 // illegal // Scientific notation 15E12 32E-6 26.176_45_e-12

25 String Constants A sequence of characters enclosed by double quotes ("") Can only be specified in a single line Each character is represented as an 8-bit ASCII code

26 Syllabus Objectives Dataflow modeling Operands Operators Constants
Data types Operators

27 Data Types Nets Variables Any hardware connection points
Any data storage elements

28 Types of Variable Data Types
reg integer time real realtime

29 The reg Variable Hold a value between assignments
May be used to model hardware registers Examples reg a, b; reg [7:0] data_a; reg [0:7] data_b; reg signed [7:0] d;

30 The integer Variable Contains integer values Has at least 32 bits
Is treated as a signed reg variable with the LSB being bit 0 integer i, j; integer data[7:0];

31 The time Variable Used for storing and manipulating simulation time
Used in conjunction with the $time system task Only unsigned value and at least 64 bits, with the LSB being bit 0 time events; time current_time;

32 The real and realtime Variables
Cannot use range declaration Defaulted to zero (0.0) real events; realtime current_time;

33 Vectors A vector = multiple bit width A scalar = 1-bit vector
[high:low] or [low:high] The leftmost bit is the MSB include nets and reg data types A scalar = 1-bit vector

34 Bit-Select and Part-Select
integer and time are allowed real and realtime are not allowed Constant part select: data_bus[3:0], bus[3] Variable part select: [<starting_bit>+:width]: data_bus[8+:8] [<starting_bit>-:width]: data_bus[15-:8]

35 Array and Memory Elements
All net and variable data types are allowed An array element can be a scalar or a vector wire a[3:0]; reg d[7:0]; wire [7:0] x[3:0]; reg [31:0] y[15:0]; integer states [3:0]; time current[5:0];

36 Memory Memory Reference model ROM, RAM, or register files
a whole word or a portion of a word of memory reg [7:0] mema [7:0]; reg [7:0] memb [3:0][3:0]; wire sum [7:0][3:0]; mema[4][3] mema[5][7:4] memb[3][1][1:0] sum[5][0]

37 Syllabus Objectives Dataflow modeling Operands Operators
Bitwise operators Arithmetic operators Concatenation/replication operators Reduction operators Logical operators Relational/equality operators Shift operators Conditional operator

38 Bitwise Operators A bit-by-bit operation A z is treated as x
The shorter operand is zero-extended

39 An Example --- A 4-to-1 MUX
// using basic and, or , not logic operators assign out = (~s1 & ~s0 & i0) | (~s1 & s0 & i1) | (s1 & ~s0 & i2) | (s1 & s0 & i3) ;

40 Syllabus Objectives Dataflow modeling Operands Operators
Bitwise operators Arithmetic operators Concatenation/replication operators Reduction operators Logical operators Relational/equality operators Shift operators Conditional operator

41 Arithmetic Operators The result is x if any operand bit has a value x
Negative numbers are represented as 2’s complement

42 Syllabus Objectives Dataflow modeling Operands Operators
Bitwise operators Arithmetic operators Concatenation/replication operators Reduction operators Logical operators Relational/equality operators Shift operators Conditional operator

43 Concatenation/Replication Operators
Concatenation operator y = {a, b[0], c[1]}; Replication operator y = {a, {4{b[0]}}, c[1]};

44 An Example --- A 4-Bit Full Adder
// specify the function of a 4-bit adder assign {c_out, sum} = x + y + c_in;

45 A 4-Bit Two’s Complement Adder
// specify the function of a two's complement adder assign t = y ^ {4{c_in}}; assign {c_out, sum} = x + t + c_in;

46 Syllabus Objectives Dataflow modeling Operands Operators
Bitwise operators Arithmetic operators Concatenation/replication operators Reduction operators Logical operators Relational/equality operators Shift operators Conditional operator

47 Reduction Operators Perform only on one vector operand
Carry out a bit-wise operation Yield a 1-bit result Work bit by bit from right to left

48 A 9-Bit Parity Generator
// dataflow modeling using reduction operator assign ep = ^x; // even parity generator assign op = ~ep; // odd parity generator

49 An All-Bit-Zero/One Detector
// dataflow modeling assign zero = ~(|x); // all-bit zero assign one = &x; // all-bit one

50 Syllabus Objectives Dataflow modeling Operands Operators
Bitwise operators Arithmetic operators Concatenation/replication operators Reduction operators Logical operators Relational/equality operators Shift operators Conditional operator

51 Logical Operators Always evaluate to a 1-bit value, 0, 1, or x
The result is x (a false condition) if any operand bit is x or z

52 Syllabus Objectives Dataflow modeling Operands Operators
Bitwise operators Arithmetic operators Concatenation/replication operators Reduction operators Logical operators Relational/equality operators Shift operators Conditional operator

53 Relational Operators The result is 1 if the expression is true and 0 if the expression is false Return x if any operand bit is x or z

54 Equality Operators Compare the two operands bit by bit
The shorter operand is zero-extended Return 1 if the expression is true and 0 if the expression is false

55 Equality Operators The operators (==, !=) The operators (===, !==)
yield an x if any operand bit is x or z The operators (===, !==) yield a 1 if the two operands exactly match 0 if the two operands not exactly match

56 A 4-B Magnitude Comparator
// dataflow modeling using relation operators assign Oaeqb = (a == b) && (Iaeqb == 1); // = assign Oagtb = (a > b) || ((a == b)&& (Iagtb == 1)); // > assign Oaltb = (a < b) || ((a == b)&& (Ialtb == 1)); // <

57 Syllabus Objectives Dataflow modeling Operands Operators
Bitwise operators Arithmetic operators Concatenation/replication operators Reduction operators Logical operators Relational/equality operators Shift operators Conditional operator

58 Shift Operators Logical shift operators Arithmetic shift operators

59 An Example of Shift Operators
input signed [3:0] x; output [3:0] y; output signed [3:0] z; assign y = x >> 1; assign z = x >>> 1;

60 Syllabus Objectives Dataflow modeling Operands Operators
Bitwise operators Arithmetic operators Concatenation/replication operators Reduction operators Logical operators Relational/equality operators Shift operators Conditional operator

61 The Conditional Operator
Usage: condition_expr ? true_expr: false_expr; If condition_expr = x or z: the result = true_expr & false_expr (0 and 0 gets 0, 1 and 1 gets 1, others gets x ) For example assign out = selection ? in_1: in_0;

62 An Example --- A 4-to-1 MUX
// using conditional operator (?:) assign out = s1 ? ( s0 ? i3 : i2) : (s0 ? i1 : i0) ;

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